Trench multilevel contact to a 3D memory array and method of making thereof

Patent metadata

Field	Value
Publication number	US-9230905-B2
Application number	US-201414150162-A
Country	US
Kind code	B2
Filing date	Jan 8, 2014
Priority date	Jan 8, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses. A second electrically conductive layer in the stack different from the first electrically conductive layer may be a topmost layer in a laterally central portion of a second one of the plurality of recesses.

First claim

What is claimed is:

1. A multilevel device, comprising:
at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base, wherein:
each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack;
the base comprises a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses;
the electrically conductive layers in the stack are substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base;
a first electrically conductive layer in the stack is a topmost layer in a laterally central portion of a first one of the plurality of recesses; and
a second electrically conductive layer in the stack different from the first electrically conductive layer is a topmost layer in a laterally central portion of a second one of the plurality of recesses.

2. The device of claim 1 , wherein the base further comprises a substantially flat unraised portion.

3. The device of claim 1 , wherein at least one of the plurality of recesses comprises a trench.

4. The device of claim 1 , wherein the raised portion comprises a plurality of pillars, and at least one of the plurality of recesses comprises a canyon defined by the plurality of pillars.

5. The device of claim 3 , wherein the plurality of pillars comprises at least four pillars, and wherein the respective laterally central portion of the recess is a point defined by an intersection of a first line extending laterally between a first pair of the at least four pillars and second line extending laterally between a second pair of the at least four pillars.

6. The device of claim 1 , wherein the first recess contains a portion of each one of the electrically conductive layers in the stack.

7. The device of claim 6 , wherein the second recess contains a portion of fewer than all of the electrically conductive layers in the stack.

8. The device of claim 7 , further comprising:
an overlayer overlaying the stack and the base, wherein the overlayer is in contact with one or more top surfaces of the raised portion of the base;
a first via connection that extends vertically through the overlayer and contacts the first electrically conductive layer at the laterally central portion of the first recess; and
a second via connection that extends vertically through the overlayer and contacts the second electrically conductive layer at the laterally central portion of the second recess;
wherein the first via connection is in electrical contact with the first electrically conductive layer, and electrically insulated from all other electrically conductive layers in the stack; and
wherein the second via connection is in electrical contact with the second electrically conductive layer, and is electrically insulated from all other electrically conductive layers in the stack.

9. The device of claim 8 , wherein:
the first electrically conductive layer extends laterally past the first via connection at the location of contact between the first electrically conductive layer and the first via connection; and
the second electrically conductive layer extends laterally past the second via connection at the location of contact between the second electrically conductive layer and the second via connection.

10. The device of claim 9 , wherein:
tops of the plurality of electrically conductive and insulting layers in the stack are removed in each of the plurality of recesses to expose sidewalls of a respective one of the electrically conductive layers; and
a respective one of the first and second via connections contacts sidewalls of the respective first and second of the plurality of electrically conductive layers in respective first and second recesses.

11. The device of claim 7 , wherein:
the stack comprises N layers l n where n is any integer where 1≦n≦N, and N is a positive integer greater than 2;
the base comprises N recesses r n ;
a recess r n contains a portion of the first n bottommost electrically conductive layers in the stack;
a layer l n is the topmost electrically conductive layer in a laterally central portion recess r n .

12. The device of claim 9 , further comprising N via connections v n ;
wherein the overlayer is in contact with one or more top surfaces of the raised portion of the base; and
wherein a via connection v n extends vertically through the overlayer to contact the electrically conductive layer l n in the laterally central portion of the recess r n .

13. The device of claim 12 , wherein N is greater than 3.

14. The device of claim 1 , wherein:
the device region comprises a 3D ReRAM device; and
at least one of the electrically conductive layers in the stack comprises or is electrically connected to a word line of the 3D ReRAM device.

15. The device of claim 1 , wherein:
the device region comprises a vertical NAND memory device; and
at least one of the electrically conductive layers in the stack comprises or is electrically connected to a word line of vertical NAND memory device.

16. A method of making multilevel contacts, comprising:
(a) providing an in-process multilevel device comprising at least one device region and at least one contact region;
(b) forming a base in the contact region comprising a raised portion and plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses;
(c) forming a conformal stack of an alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base, wherein each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack; and
(d) removing material from the stack that overlays the raised portion of the base to expose one or more top surfaces of the raised portion of the base, wherein portions of the stack contained in the recesses are not removed.

17. The method of claim 16 , wherein step (c) comprises:
filling a first recess with portions of all of the plurality of electrically conductive layers in the stack; and
filling a second recess that is laterally smaller that the first recess with portions of all of the electrically conductive layers in the stack except for an uppermost first electrically conductive layer in the stack.

18. The method of claim 17 , wherein step (c) further comprises:
filling a third recess that is laterally smaller than the second recess with portions of all of the plurality of electrically conductive layers in the stack except for the two uppermost electrically conductive layers in the stack.

19. The method of claim 17 , wherein step (d) comprises:
exposing a portion of the uppermost first electrically conductive layer in the stack in a laterally central portion of first recess; and
exposing a portion of a second electrically conductive layer in the stack underlying the uppermost first electrically conductive layer in the stack in a laterally central portion the second recess.

20. The method of claim 18 , wherein step (d) comprises:
exposing a portion of the uppermost first electrically conductive layer in the stack in a latera

Assignees

• Sandisk 3D Llc

Inventors

• Takaki Seje
• Sano Michiaki
• Chen Zhen

Classifications

• H10W20/0636

  the conductive members being on sidewalls · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title