Method for evaluating semiconductor wafer and apparatus for evaluating semiconductor wafer

Patent metadata

Field	Value
Publication number	US-9746400-B2
Application number	US-201314395907-A
Country	US
Kind code	B2
Filing date	Apr 15, 2013
Priority date	May 7, 2012
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

The present invention provides a method for evaluating a semiconductor wafer concerning a breaking strength of a notch portion of the semiconductor wafer, comprising: applying a load to a notch portion of the semiconductor wafer to be evaluated toward the center of the wafer such that the notch portion of the semiconductor wafer is broken; and evaluating the breaking strength of the notch portion. The present invention provides a method and an apparatus for evaluating a semiconductor wafer that can evaluate the breaking strength of a notch portion of a semiconductor wafer with higher precision and higher sensitivity.

First claim

The invention claimed is:

1. A method for evaluating a semiconductor wafer concerning a breaking strength of a notch portion of the semiconductor wafer, comprising:
applying a load to the notch portion of the semiconductor wafer to be evaluated toward the center of the wafer such that the notch portion of the semiconductor wafer is broken; and
evaluating the breaking strength of the notch portion.

2. The method for evaluating a semiconductor wafer according to claim 1 , wherein the load is applied by pressing a pin against the notch portion.

3. The method for evaluating a semiconductor wafer according to claim 2 , wherein the load is applied in a manner of a vertical static pressure load or a horizontal static pressure load.

4. The method for evaluating a semiconductor wafer according to claim 3 , wherein the breaking strength of the notch portion is evaluated in such a manner that a test piece including the notch portion is cut from the semiconductor wafer to be evaluated; the test piece is interposed and held between a pair of holding jigs; and a load is applied to the notch portion of the held test piece.

5. The method for evaluating a semiconductor wafer according to claim 4 , wherein each of the pair of holding jigs is provided with a cut through which a vicinity of the notch portion is exposed.

6. The method for evaluating a semiconductor wafer according to claim 5 , further comprising: in addition to the evaluation of the breaking strength of the notch portion of the semiconductor wafer by using the test piece including the notch portion, cutting a test piece including no notch portion from the semiconductor wafer to be evaluated; applying a load to an edge of the test piece including no notch portion; evaluating a breaking strength of the edge of the semiconductor wafer; and comparing evaluation results of the notch portion and the edge.

7. The method for evaluating a semiconductor wafer according to claim 2 , wherein the breaking strength of the notch portion is evaluated in such a manner that a test piece including the notch portion is cut from the semiconductor wafer to be evaluated; the test piece is interposed and held between a pair of holding jigs; and a load is applied to the notch portion of the held test piece.

8. The method for evaluating a semiconductor wafer according to claim 1 , wherein the load is applied in a manner of a vertical static pressure load or a horizontal static pressure load.

9. The method for evaluating a semiconductor wafer according to claim 8 , wherein the breaking strength of the notch portion is evaluated in such a manner that a test piece including the notch portion is cut from the semiconductor wafer to be evaluated; the test piece is interposed and held between a pair of holding jigs; and a load is applied to the notch portion of the held test piece.

10. The method for evaluating a semiconductor wafer according to claim 1 , wherein the breaking strength of the notch portion is evaluated in such a manner that a test piece including the notch portion is cut from the semiconductor wafer to be evaluated; the test piece is interposed and held between a pair of holding jigs; and a load is applied to the notch portion of the held test piece.

11. The method for evaluating a semiconductor wafer according to claim 10 , wherein each of the pair of holding jigs is provided with a cut through which a vicinity of the notch portion is exposed.

12. The method for evaluating a semiconductor wafer according to claim 10 , further comprising: in addition to the evaluation of the breaking strength of the notch portion of the semiconductor wafer by using the test piece including the notch portion, cutting a test piece including no notch portion from the semiconductor wafer to be evaluated; applying a load to an edge of the test piece including no notch portion; evaluating a breaking strength of the edge of the semiconductor wafer; and comparing evaluation results of the notch portion and the edge.

13. An apparatus for evaluating a semiconductor wafer, the apparatus being configured to evaluate a breaking strength of a notch portion of the semiconductor wafer comprising
a load applying device configured to apply a load to the semiconductor wafer to be evaluated, the load applying device applying the load in a direction from the notch portion to the center of the wafer and being capable of breaking the notch portion by the load.

14. The apparatus for evaluating a semiconductor wafer according to claim 13 , wherein the load applying device includes a pin configured to apply the load by being pressed against the notch portion.

15. The apparatus for evaluating a semiconductor wafer according to claim 14 , wherein the load applying device is configured to apply the load in a manner of a vertical static pressure load or a horizontal static pressure load.

16. The apparatus for evaluating a semiconductor wafer according to claim 15 ,
further comprising a pair of holding jigs configured to interpose and hold a test piece of the semiconductor wafer to be evaluated therebetween, the test piece including the notch portion,
wherein the load applying device is configured to apply the load to the test piece held by the pair of holding jigs.

17. The apparatus for evaluating a semiconductor wafer according to claim 16 , wherein each of the pair of holding jigs is provided with a cut through which a vicinity of the notch portion is exposed.

18. The apparatus for evaluating a semiconductor wafer according to claim 17 , wherein the load applying device is further capable of applying a load to an edge of a test piece and breaking the edge by the load, the test piece including no notch portion and being cut from the semiconductor wafer to be evaluated.

19. The apparatus for evaluating a semiconductor wafer according to claim 14 ,
further comprising a pair of holding jigs configured to interpose and hold a test piece of the semiconductor wafer to be evaluated therebetween, the test piece including the notch portion,
wherein the load applying device is configured to apply the load to the test piece held by the pair of holding jigs.

20. The apparatus for evaluating a semiconductor wafer according to claim 13 , wherein the load applying device is configured to apply the load in a manner of a vertical static pressure load or a horizontal static pressure load.

21. The apparatus for evaluating a semiconductor wafer according to claim 20 ,
further comprising a pair of holding jigs configured to interpose and hold a test piece of the semiconductor wafer to be evaluated therebetween, the test piece including the notch portion,
wherein the load applying device is configured to apply the load to the test piece held by the pair of holding jigs.

22. The apparatus for evaluating a semiconductor wafer according to claim 13 ,
further comprising a pair of holding jigs configured to interpose and hold a test piece of the semiconductor wafer to be evaluated therebetween, the test piece including the notch portion,
wherein the load applying device is configured to apply the load to the test piece held by the pair of holding jigs.

23. The apparatus for evaluating a semiconductor wafer according to claim 22 , wherein each of the pair of holding jigs is provided with a cut through which a vicinity of the notch portion is exposed.

24. The apparatus for evaluating a semiconductor wafer according to claim 22 , wherein the load applying device is further capabl

Assignees

• Shinetsu Handotai Kk

Inventors

• Sagara Kazuhiro

Classifications

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G01N2203/0282

  Two dimensional, e.g. tapes, webs, sheets, strips, disks or membranes · CPC title

• G01N3/02 Primary

  Details · CPC title

• G01N2203/006

  Crack, flaws, fracture or rupture · CPC title

• G01N3/42

  by performing impressions under a steady load by indentors, e.g. sphere, pyramid (G01N3/54 takes precedence) · CPC title