Systems and methods for CMOS-integrated junction field effect transistors for dense and low-noise bioelectronic platforms

Patent metadata

Field	Value
Publication number	US-9741870-B2
Application number	US-201514681753-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Oct 17, 2012
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A complementary metal oxide semiconductor (CMOS)-integrated junction field effect transistor (JFET) has reduced scale and reduced noise. An exemplary JFET has a substrate layer of one dopant type with a gate layer of that dopant type disposed on the substrate, a depletion channel of a second dopant type disposed on the first gate layer, and a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor. The second gate layer can separate the depletion channel from the surface, and the depletion channel separates the first gate layer from the second gate layer.

First claim

The invention claimed is:

1. An integrated junction field effect transistor formed as a complementary metal oxide semiconductor, comprising:
a substrate layer of a first dopant type;
an isolation well of a second dopant type disposed above the substrate;
a first gate layer of the first dopant type disposed above the isolation well;
a depletion channel of the second dopant type disposed above the first gate layer;
a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor, the second gate layer separating the depletion channel from the surface, and the depletion channel separating the first gate layer from the second gate layer; and
a drain contact and a source contact, each disposed proximate the surface and in electrical communication with the depletion channel, wherein each of the source and drain contacts are disposed proximate and abut a layer formed between the second gate layer and each of the source and drain contacts and configured to reduce flicker noise.

2. The transistor as claimed in claim 1 , wherein the isolation well of the second dopant type is disposed between and separating the substrate layer and the first gate layer.

3. The transistor as claimed in claim 1 , further including shallow trench isolation between the second gate layer and each of the source and drain contacts.

4. The transistor as claimed in claim 1 , wherein the first dopant type is P-type and the second dopant type is N-type.

5. The transistor as claimed in claim 1 , wherein the first dopant type is N-type and the second open type is P-type.

6. A plurality of transistors as claimed in claim 1 , configured as an array.

7. A method of making a junction field effect transistor using a complementary metal oxide semiconductor (CMOS) process, comprising:
providing a substrate layer of a first dopant type;
forming an isolation well of the second dopant type above the substrate;
forming a first gate layer of the first dopant type above the isolation well;
forming a depletion channel of the second dopant type above the first gate layer;
forming a second gate layer of the first dopant type above the depletion channel and proximate a surface of the transistor, the second gate layer separating the depletion channel from the surface, and the depletion channel separating the first gate layer from the second gate layer;
forming a drain contact and a source contact, each disposed proximate the surface and in electrical communication with the depletion channel; and
forming a low doping layer between the second gate layer and each of the source and drain contacts, wherein the low doping layer is disposed proximate and abuts each of the source and drain contacts and is configured to reduce flicker noise.

8. A method of making the transistor as claimed in claim 7 , wherein an isolation well of the second dopant type is disposed between and separating the substrate layer and the first gate layer.

9. A method of making the transistor as claimed in claim 7 , wherein the transistor is formed using a 180 nm process.

10. A method of making the transistor as claimed in claim 7 , wherein the first dopant type is P-type and the second dopant type is N-type.

11. A method of making the transistor as claimed in claim 7 , wherein the first dopant type is N-type and the second open type is P-type.

12. A method of making the plurality of transistors as claimed in claim 7 , configured as an array.

13. The transistor of claim 1 , wherein the low doping layer comprises polysilicon.

14. The transistor of claim 1 , wherein the low doping layer comprises an ohmic contact pattern (OP) mask.

Assignees

• Univ Columbia

Inventors

• Shepard Kenneth L
• Rosenstein Jacob
• Field Ryan Michael
• Fleischer Dan

Classifications

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H01L27/098

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/808 Primary

  Electricity · mapped topic