Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9190331-B2
Application number	US-201414505102-A
Country	US
Kind code	B2
Filing date	Oct 2, 2014
Priority date	Nov 24, 2011
Publication date	Nov 17, 2015
Grant date	Nov 17, 2015

Abstract

A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a fin projecting upwardly from or through an upper surface of the substrate, the fin including a first semiconductor layer portion formed from a corresponding first semiconductor material, the fin being interposed between and longitudinally extending between a semiconductive source region portion and a semiconductive drain region portion;
wherein the fin includes a semiconductive channel region joining the…

Assignees

• Semiconductor Mfg Int Shanghai
• Semiconductor Mfg Int Beijing

Inventors

• Fumitake Mieno

Classifications

• H10P30/22

  Electricity · mapped topic

• H10P30/20

  Electricity · mapped topic

• H10D86/215

  Electricity · mapped topic

• H10D84/0123

  Electricity · mapped topic

• H10D84/87

  Electricity · mapped topic