Data storage device and operating method thereof

Patent metadata

Field	Value
Publication number	US-2016253266-A1
Application number	US-201514747850-A
Country	US
Kind code	A1
Filing date	Jun 23, 2015
Priority date	Feb 26, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

A data storage device includes a plurality of memory apparatuses, a searching unit configured to search for “k” physical addresses mapped to “k” continuous logical addresses, and a processor configured to determine numerical consecutiveness of “i” logical addresses mapped to “i” continuous physical addresses consecutive to an K th physical address of the “k” physical addresses, and transmit a first pre-read command with respect to a first pre-read memory area corresponding to the “i” continuous physical addresses and first read-estimated physical addresses consecutive to the “i” continuous physical addresses when the numerical consecutiveness is admitted.

First claim

What is claimed is:

1 . A data storage device comprising:
a plurality of memory apparatuses; a searching unit suitable for searching for “k” number of physical addresses mapped to “k” number of numerically consecutive logical addresses in a mapping table; and a processor suitable for: determining whether “i” number of logical addresses are numerically consecutive to the “k” logical addresses, wherein the “i” logical addresses are mapped to “i” number of physical addresses that are numerically consecutive to the “k” physical addresses, and transmitting a first pre-read command along with first pre-read physical addresses for access to a first pre-read memory area when the “i” logical addresses are numerically consecutive to the “k” logical addresses, wherein the first pre-read physical addresses include the physical addresses and one or more first read-estimated physical “i” addresses that are numerically consecutive to the “i” physical addresses.

2 . The data storage device according to claim 1 , wherein the processor further transmits a normal read command along with the “k” physical addresses for access to a normal memory area.

3 . The data storage device according to claim 2 , wherein the first pre-read memory area and the normal memory area are included in different memory apparatuses.

4 . The data storage device according to claim 1 , wherein, when the “i” number of logical addresses are numerically consecutive to the “k” logical addresses, the searching unit subsequently searches for another “k” number of physical addresses mapped to another “k” number of consecutive logical addresses that are numerically consecutive to the “i” logical addresses.

5 . The data storage device according to claim 4 , wherein the processor determines validity of data pre-read from the pre-read area based on a subsequent search result.

6 . The data storage device according to claim 5 , wherein the processor performs the validity determination by determining whether a first “k-i” number of physical addresses among the subsequently searched “k” physical addresses coincide with the first read-estimated physical addresses.

7 . The data storage device according to claim 4 , wherein the processor further transmits a second pre-read command along with second pre-read physical addresses for access to a second pre-read memory area, wherein the second pre-read physical addresses include “i” number of physical addresses subsequent to a first “k-i” number of physical addresses, among the subsequently searched “k” physical addresses, and one or more second read-estimated physical addresses that are numerically consecutive to the “i” physical addresses, subsequent to the first “k-i” number of physical addresses.

8 . The data storage device according to claim 1 , wherein the processor further refers to the mapping table in order to determine the numerical consecutiveness.

9 . An operation method of a data storage device, comprising:
searching for “k” number of physical addresses mapped to “k” number of numerically consecutive logical addresses in a mapping table; determining whether “i” number of logical addresses are numerically consecutive to the “k” logical addresses, wherein the “i” logical addresses are mapped to “i” number of physical addresses that are numerically consecutive to the “k” physical addresses; and transmitting a first pre-read command along with first pre-read physical addresses for access to a first pre-read memory area when the “i” logical addresses are numerically consecutive to the “k” logical addresses, wherein the first pre-read physical addresses include the “i” physical addresses and one or more first read-estimated physical addresses that are numerically consecutive to the “i” physical addresses.

10 . The operation method according to claim 9 , further comprising:
transmitting a normal read command along with the “k” physical addresses for access to a normal memory area.

11 . The operation method according to claim 10 , wherein the first pre-read memory area and the normal memory area are located in different memory apparatuses.

12 . The operation method according to claim 9 , further comprising subsequently searching for another “k” number of physical addresses mapped to another “k” number of consecutive logical addresses that are numerically consecutive to the “i” logical addresses when the “i” number of logical addresses are numerically consecutive to the “k” logical addresses.

13 . The operation method according to claim 12 , further comprising determining validity of data pre-read from the pre-read area based on a subsequent search result.

14 . The operation method according to claim 13 , wherein the determining of the validity comprises determining whether a first “k-i” number of physical addresses among the subsequently searched “k” physical addresses coincide with the first read-estimated physical addresses.

15 . The operation method according to claim 12 , further comprising: transmitting a second pre-read command along with second pre-read physical addresses for access to a second pre-read memory area, wherein the second pre-read physical addresses include “i” number of physical addresses subsequent to a first “k-i” number of physical addresses among the subsequently searched “k” physical addresses and one or more second read-estimated physical addresses numerically consecutive to the “i” physical addresses that are subsequent to the first “k-i” number of physical addresses.

16 . A data storage device comprising:
a controller suitable for: searching for a first physical address mapped to a read-requested first logical address, determining whether a second logical address is numerically consecutive to the first logical address, wherein the second logical address is mapped to a second physical address that is numerically consecutive to the first physical address, and transmitting a first pre-read command along with the second physical address for access to a first pre-read memory area when the second logical address is numerically consecutive to the first logical address; and a first memory apparatus suitable for performing a read operation to the first pre-read memory area in response to the first pre-read command and the second physical address.

17 . The data storage device according to claim 16 ,
further comprising a second memory apparatus, wherein the controller further transmits a normal read command along with the first physical address for access to a normal memory area of the second memory apparatus.

18 . The data storage device according to claim 16 , wherein the first pre-read memory area corresponds to the second physical address and physical addresses numerically consecutive to the second physical address.

19 . The data storage device according to claim 16 , wherein, when the second logical address is numerically consecutive to the first logical address, the controller further:
subsequently searches for a third physical address mapped to a third logical address that is numerically consecutive to the second logical address, and determines validity of data pre-read from he first pre-read area based on a subsequent search result.

20 . The data storage device according to claim 19 , wherein the controller further transmits a second pre-read command along with a fourth physical address, subsequent to the third physical address, for access to a second pre-read memory area, wherein the second pre-read memory area corresponds to the fourth physical addres

Assignees

• Sk Hynix Inc

Inventors

• Park Jeen

Classifications

• G06F2212/171

  Portable consumer electronics, e.g. mobile phone · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F12/0862

  with prefetch · CPC title