Method and Apparatus for Querying Physical Memory Address

Patent metadata

Field	Value
Publication number	US-2016170904-A1
Application number	US-201615047938-A
Country	US
Kind code	A1
Filing date	Feb 19, 2016
Priority date	Aug 20, 2013
Publication date	Jun 16, 2016
Grant date	—

Abstract

A method and an apparatus for querying a physical memory address where the method includes storing, into a prefetch buffer, page table entries of a second thread that is to perform addressing that are stored in a standby buffer, where the standby buffer stores page table entries that are not queried within a set time in a translation lookaside buffer (TLB), receiving a memory addressing request message that carries a virtual address and is sent by the second thread, and querying, in the TLB and the prefetch buffer, a corresponding physical address according to the virtual address.

First claim

What is claimed is:

1 . A method for querying a physical address to access a memory, comprising:
storing, into a prefetch buffer, page table entries of a second thread that are stored in a standby buffer when determining that a memory addressing operation will be switched from a first thread to the second thread within a future set time, wherein the standby buffer stores page table entries that are not queried within a set time in a translation lookaside buffer (TLB); receiving a memory addressing request message corresponding to the second thread, wherein the memory addressing request message carries a virtual address; and querying, according to the virtual address, in page table entries stored in the TLB and the page table entries stored in the prefetch buffer, a physical address corresponding to the virtual address.

2 . The method according to claim 1 , wherein querying, according to the virtual address, in page table entries stored in the TLB and the page table entries stored in the prefetch buffer, the physical address corresponding to the virtual address further comprises accessing the memory using a first physical address, when the first physical address corresponding to the virtual address exists in the TLB.

3 . The method according to claim 1 , wherein querying, according to the virtual address, in page table entries stored in the TLB and the page table entries stored in the prefetch buffer, the physical address corresponding to the virtual address further comprises accessing the memory using a second physical address, when there is no physical address corresponding to the virtual address existing in the TLB, but the second physical address corresponding to the virtual address exists in the prefetch buffer.

4 . The method according to claim 1 , wherein querying, according to the virtual address, in page table entries stored in the TLB and the page table entries stored in the prefetch buffer, the physical address corresponding to the virtual address further comprises querying the memory for a third physical address corresponding to the virtual address, when there is no physical address corresponding to the virtual address exist in the TLB and there in no physical address corresponding to the virtual address exist in the prefetch buffer.

5 . The method according to claim 3 , further comprising storing, into the TLB, a page table entry in the prefetch buffer that is corresponding to the virtual address and the second physical address.

6 . The method according to claim 5 , further comprising deleting, from the prefetch buffer, the page table entry that is corresponding to the virtual address and the second physical address.

7 . The method according to claim 4 , further comprising storing, into the TLB, another page table entry found in the memory that is corresponding to the virtual address and the third physical address.

8 . The method according to claim 1 , wherein before storing, into the prefetch buffer, page table entries of the second thread that are stored in the standby buffer when determining that the memory addressing operation will be switched from the first thread to the second thread within the future set time, wherein the standby buffer stores page table entries that are not queried within the set time in the TLB, the method further comprises storing, into the standby buffer, the page table entries that are not queried within the set time in the TLB.

9 . The method according to claim 8 , wherein after storing, into the standby buffer, the page table entries that are not queried within the set time in the TLB, the method further comprises deleting, from the TLB, the page table entries that are not queried within the set time when a quantity of page table entries stored in the TLB exceeds a storage capacity of the TLB.

10 . The method according to claim 8 , wherein after storing, the method further comprises deleting another page table entry with a longest storage time from the standby buffer, when a quantity of page table entries stored in the standby buffer exceeds a storage capacity of the standby buffer.

11 . A multi-threaded processor for a computer system comprising a memory coupled to the multi-threaded processor, wherein the multi-threaded processor comprises:
a translation lookaside buffer (TLB); a prefetch buffer; a standby buffer, coupled to the TLB and the prefetch buffer, and configured to store page table entries that are not queried within a set time in the TLB; a memory manager coupled to the TLB, the prefetch buffer and the standby buffer, wherein the memory manager is configured to:
store, into the prefetch buffer, page table entries of a second thread that are stored in the standby buffer when determining, according to a preset thread switching policy, that a memory addressing operation will be switched from a first thread to the second thread within a future set time, wherein the standby buffer stores page table entries that are not queried within a set time in the TLB;
receive a memory addressing request message corresponding to the second thread, wherein the memory addressing request message carries a virtual address; and
query, according to the virtual address, in page table entries stored in the TLB and the page table entries stored in the prefetch buffer, a physical address corresponding to the virtual address.

12 . The multi-threaded processor according to claim 11 , wherein the memory manager is further configured to access the memory using a first physical address, when the first physical address corresponding to the virtual address exists in the TLB.

13 . The multi-threaded processor according to claim 11 , wherein the memory manager is further configured to access the memory using a second physical address, when there is no physical address corresponding to the virtual address existing in the TLB, but the second physical address corresponding to the virtual address exists in the prefetch buffer.

14 . The multi-threaded processor according to claim 10 , wherein the memory manager is further configured to query the memory for a third physical address corresponding to the virtual address, when there is no physical address corresponding to the virtual address existing in the TLB and there is no physical address corresponding to the virtual address existing in the prefetch buffer.

15 . The multi-threaded processor according to claim 13 , wherein the memory manager is further configured to store, into the TLB, a page table entry in the prefetch buffer that is corresponding to the virtual address and the second physical address.

16 . The multi-threaded processor according to claim 15 , wherein the memory manager is further configured to delete, from the prefetch buffer, the page table entry that is corresponding to the virtual address and the second physical address.

17 . The multi-threaded processor according to claim 14 , wherein the memory manager is further configured to store, into the TLB, another page table entry found in the memory that is corresponding to the virtual address and the third physical address.

18 . The multi-threaded processor according to claim 11 , wherein the memory manager is further configured to store, into the standby buffer, the page table entries that are not queried within the set time in the TLB.

19 . The multi-threaded processor according to claim 18 , wherein the memory manager is further configured to delete, from the TLB, the page table entries that are not queried within the set time when a quantity of page table entries stored

Assignees

• Huawei Tech Co Ltd

Inventors

• Guo Xubin
• Hou Rui
• Feng Yujing
• Su Dongfeng

Classifications

• G06F12/0842 Primary

  for multiprocessing or multitasking · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F2212/6022

  Using a prefetch buffer or dedicated prefetch cache · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/1045 Primary

  associated with a data cache · CPC title