Pure boron for silicide contact

Patent metadata

Field	Value
Publication number	US-9735248-B2
Application number	US-201615248002-A
Country	US
Kind code	B2
Filing date	Aug 26, 2016
Priority date	Jul 29, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×10 21 to about 5×10 22 atoms/cm 2 .

First claim

What is claimed is:

1. A semiconductor device, comprising:
a gate disposed over a substrate;
a source region and a drain region on opposing sides of the gate; and
a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region;
wherein the interfacial layer comprises boron in an amount in a range from about 5×10 21 to about 5×10 22 atoms/cm 2 .

2. The semiconductor device of claim 1 , wherein the pair of trench contacts is positioned within a recessed region of the epitaxial contacts.

3. The semiconductor device of claim 1 , wherein the interfacial layer has a thickness in a range from about 0.5 to about 2 nanometers (nm).

4. The semiconductor device of claim 1 , wherein the trench contacts have sidewalls that contact the interfacial layer.

5. The semiconductor device of claim 1 , wherein the semiconductor device is a p-type field effect transistor (PFET).

6. The semiconductor device of claim 1 , wherein the trench contact comprises a high-k dielectric material.

7. The semiconductor device of claim 6 , wherein the high-k dielectric material contacts the interfacial layer.

8. The semiconductor device of claim 6 , wherein the trench contact further comprises a conductive metal.

9. The semiconductor device of claim 8 , wherein the conductive metal is tungsten, aluminum, platinum, gold, or any combination thereof.

10. The semiconductor device of claim 6 , wherein the high-k dielectric material is HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , a pervoskite oxide, or any combination thereof.

11. The semiconductor device of claim 1 , wherein the trench contacts have a base that contacts the interfacial layer.

12. The semiconductor device of claim 1 , wherein the interfacial layer comprises at least 99 atomic % boron.

13. The semiconductor device of claim 1 , wherein the interfacial layer comprises boron in an amount in a range from about 1×10 22 to about 3×10 22 atoms/cm 2 .

14. The semiconductor device of claim 1 , wherein the interfacial layer comprises 100 atomic % boron.

15. The semiconductor device of claim 1 , wherein the interfacial layer comprises at least 98 atomic % boron.

16. The semiconductor device of claim 1 , wherein the substrate comprises silicon.

17. The semiconductor device of claim 1 , wherein the substrate comprises silicon germanium.

18. The semiconductor device of claim 1 , wherein the source region comprises epitaxial growth.

19. The semiconductor device of claim 1 , wherein the drain region comprises epitaxial growth.

20. The semiconductor device of claim 1 , wherein the interfacial layer has a thickness in a range from about 1 nm to about 1.5 nm.

Assignees

• IBM

Inventors

• Chen Chia-Yu
• Liu Zuoguang
• Mehta Sanjay C
• Yamashita Tenko

Classifications

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P32/1404

  using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase · CPC title

• H10P32/171

  being group IV material · CPC title