Integration of hybrid germanium and group III-V contact epilayer in CMOS

Patent metadata

Field	Value
Publication number	US-9543216-B2
Application number	US-201514731480-A
Country	US
Kind code	B2
Filing date	Jun 5, 2015
Priority date	Jun 5, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region.

First claim

What is claimed is:

1. A method comprising:
forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions;
depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches;
removing the SiN layer in the PFET region;
growing a germanium (Ge) epilayer over the source/drain regions in the PFET region;
depositing metal over the ILD and in the trenches in the NFET and PFET regions;
etching the metal in the NFET region to expose the conformal SiN layer;
removing the SiN layer in the NFET region;
growing a Group III-V epilayer over the source/drain regions in the NFET region; and
depositing metal over the ILD and in the trenches in the NFET region.

2. The method according to claim 1 , comprising:
forming the trenches through the ILD in the NFET and PFET regions concurrently.

3. The method according to claim 1 , comprising:
forming a blocking mask over the NFET region prior to removing the SiN layer in the PFET region, wherein the blocking mask comprises an organic planarization layer (OPL).

4. The method according to claim 3 , comprising:
removing the OPL prior to growing the Ge epilayer over the source/drain regions in the PFET region.

5. The method according to claim 4 , wherein the Ge epilayer comprises boron doped Ge (Ge:B).

6. The method according to claim 1 , wherein the Group III-V epilayer comprises GaAs, InP, InAs, InSb, GaSb, InGaAs, InN or AlGaAs.

7. The method according to claim 1 , comprising:
depositing a metal silicide layer prior to depositing the metal over the ILD and in the trenches in the PFET and NFET regions,
wherein the metal comprises Ti, Cu, Co or W.

8. The method according to claim 7 , further comprising:
depositing an oxide blocking mask over the PFET region prior to etching the metal in the NFET region and etching the metal silicide layer with the metal to expose the SiN layer in the NFET region.

9. The method according to claim 1 , further comprising:
removing the SiN layer in the NFET region prior to growing the Group III-V epilayer over the source/drain regions in the NFET region.

10. The method according to claim 9 , further comprising:
depositing a metal silicide layer prior to depositing the metal over the ILD and in the trenches in the NFET region.

11. The method according to claim 10 , further comprising:
planarizing the metal down to the ILD in the PFET and NFET regions concurrently.

12. The method according to claim 11 , wherein the planarizing includes chemical-mechanical planarization.

13. The method according to claim 1 , comprising forming the trenches at opposite sides of NFET and PFET gates.

14. The method according to claim 13 , wherein the NFET and PFET gates each comprise a metal gate including spacers at opposite sides of the metal gate and a siliconborocarbonitride (SiBCN) cap over the metal gate and spacers.

15. A method comprising:
forming trenches through an interlayer dielectric (ILD) deposited over source/drain regions at opposite sides of metal gates in NFET and PFET regions;
depositing a conformal silicon nitride (SiN) layer over the metal gates and in the trenches;
forming a blocking mask over the NFET region, wherein the blocking mask comprises an organic planarization layer (OPL);
removing the SiN layer in the PFET region;
removing the blocking mask;
growing a Ge:B epilayer over the source/drain regions in the PFET region;
depositing metal over the ILD and in the trenches;
etching the metal in the NFET region to expose the conformal SiN layer;
removing the SiN layer in the NFET region;
growing a Group III-V epilayer over the source/drain regions in the NFET region, the Group III-V epilayer comprising GaAs, InP, InAs, InSb, GaSb, InGaAs, InN or AlGaAs; and
depositing metal over the ILD and in the trenches in the NFET region.

Assignees

• Globalfoundries Inc

Inventors

• Niimi Hiroaki
• Xie Ruilong

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10P14/414

  of metal-silicide materials · CPC title