Embedded flash memory device with floating gate embedded in a substrate

Patent metadata

Field	Value
Publication number	US-9230977-B2
Application number	US-201313924331-A
Country	US
Kind code	B2
Filing date	Jun 21, 2013
Priority date	Jun 21, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

First claim

What is claimed is:

1. A device comprising:
a semiconductor substrate; and
an embedded flash memory device comprising:
a first gate stack comprising:
a bottom dielectric layer extending into a recess in the semiconductor substrate;
a charge storage layer over the bottom dielectric layer, wherein the charge storage layer comprises a first portion in the recess; and a second portion out of the recess;
a top dielectric layer over the charge storage layer; and
a first metal gate over the top dielectric layer; and

first source and drain regions in the semiconductor substrate, wherein the first source and drain regions are isolated from each other by a channel of the embedded flash memory device, and the first source and drain regions extend from a top surface of the semiconductor substrate into the semiconductor substrate.

2. The device of claim 1 further comprising a first high-k dielectric layer over the top dielectric layer and underlying the first metal gate.

3. The device of claim 2 , wherein the top dielectric layer comprises:
a first oxide layer;
a nitride layer over the first oxide layer; and
a second oxide layer over the nitride layer.

4. The device of claim 2 further comprising:
a non-memory transistor comprising a second gate stack, wherein the second gate stack comprises:
a dielectric layer over the semiconductor substrate;
a second high-k dielectric layer over the dielectric layer, wherein the first high-k dielectric layer and the second high-k dielectric layer are formed of a same material, and have a same thickness; and
a second metal gate over the second high-k dielectric layer, wherein the first metal gate and the second metal gate are formed of a same material, and have a same thickness.

5. The device of claim 1 further comprising a first metal capping layer overlying the top dielectric layer and underlying the first metal gate, with the first metal capping layer in physical contact with the first metal gate.

6. The device of claim 1 , wherein the embedded flash memory device is comprised in a memory array comprising a plurality of embedded flash memory devices, wherein the semiconductor substrate comprises an intermediate portion between, and coplanar with, charge storage layers of two neighboring ones of the plurality of embedded flash memory devices.

7. The device of claim 1 , wherein the embedded flash memory device is comprised in a memory array comprising a plurality of embedded flash memory devices, wherein between charge storage layers of two neighboring ones of the plurality of embedded flash memory devices, the semiconductor substrate does not include any portion therein.

8. A device comprising:
a semiconductor substrate;
an embedded flash memory device comprising a first gate stack, wherein the first gate stack comprises:
a bottom silicon oxide layer extending on sidewalls and a bottom of a recess in the semiconductor substrate;
a charge storage layer over the bottom silicon oxide layer, wherein a lower portion of the charge storage layer is embedded in the recess; and an upper portion of the charge storage layer is higher than a top surface of the semiconductor substrate;
a top oxide layer over the charge storage layer;
a first high-k dielectric layer over and contacting the top oxide layer;
a first metal capping layer over and contacting the first high-k dielectric layer; and
a first metal gate over and contacting the first metal capping layer; and

a source region and a drain region in the semiconductor substrate, wherein the source region and the drain region are isolated from each other by a channel of the embedded flash memory device, and the source region and the drain region extend from the top surface of the semiconductor substrate into the semiconductor substrate.

9. The device of claim 8 , wherein the bottom silicon oxide layer comprises a horizontal portion over and contacting the semiconductor substrate, and wherein the horizontal portion of the bottom silicon oxide layer, the first high-k dielectric layer, and the first metal capping layer are co-terminus.

10. The device of claim 8 further comprising a non-memory transistor, wherein the non-memory transistor comprises a second gate stack comprising:
an oxide layer over the semiconductor substrate;
a second high-k dielectric layer over and contacting the oxide layer, wherein the first and the second high-k dielectric layers have a same thickness, and are formed of a same material;
a second metal capping layer over and contacting the second high-k dielectric layer, wherein the first and the second metal capping layers have a same thickness, and are formed of a same material; and
a second metal gate over the second metal capping layer, wherein a top surface of the first metal gate is coplanar with a top surface of the second metal gate, and a bottom surface of the first metal gate is higher than a bottom surface of the second metal gate.

11. The device of claim 10 , wherein the non-memory transistor is an High-Voltage (HV) transistor in a high voltage device region.

12. The device of claim 10 , wherein the non-memory transistor is an Input/Output (I 0 ) transistor in an Input/output (I 0 ) device region.

13. The device of claim 10 , wherein the non-memory transistor is a core transistor in a core device region.

14. The device of claim 10 , wherein the first and the second metal capping layers comprise titanium nitride.

15. A device comprising:
a semiconductor substrate comprising a first top surface and a second top surface higher than the first top surface;
a first embedded flash memory device comprising a first gate stack, wherein the first gate stack comprises:
a bottom dielectric layer overlapping the first top surface;
a charge storage layer over the bottom dielectric layer, wherein the charge storage layer comprises a first portion lower than the second top surface, and a second portion higher than the second top surface;
a top dielectric layer over the charge storage layer;
a gate over the top dielectric layer; and
a source region and a drain region in the semiconductor substrate, wherein the source region and the drain region are isolated from each other by a channel of the first embedded flash memory device, and the source region and the drain region extend from the second top surface into the semiconductor substrate;

a non-memory transistor comprising:
a gate dielectric overlapping the second top surface of the semiconductor substrate; and
a gate electrode over the gate dielectric, wherein a top surface of the gate of the first embedded flash memory device is coplanar with a top surface of the gate electrode of the non-memory transistor.

16. The device of claim 15 further comprising a second embedded flash memory device comprising:
an additional bottom dielectric layer overlapping a third top surface of the semiconductor substrate, wherein the third top surface is coplanar with the first top surface; and
an additional charge storage layer overlapping the additional bottom dielectric layer, wherein an entire top surface of an entirety of the portion of the semiconductor substrate between the first and the second embedded flash memory devices is coplanar with the first top surface.

17. The device of claim 15 further comprising a second embedded flash memory device comprising:
an additional bottom dielectric layer overlapping a third top surface of the semiconductor substrate, wherein the third top surface is coplanar with the first top surface; and
an additional charge storage layer overlapping the additional bottom

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Wu Wei Cheng
• Chuang Harry-Hak-Lay

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title