Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016148944-A1
Application number	US-201514919083-A
Country	US
Kind code	A1
Filing date	Oct 21, 2015
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming split gate structures, each including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate, the substrate including the cell region and a logic region adjacent to the cell region; sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region; removing the metal gate film from at least a portion of the cell region and the logic region; forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed; forming a gate electrode film on the logic region and the cell region; and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region by patterning the first and second gate insulating films, the gate electrode film, and a residue of the metal gate film.

2 . The method of claim 1 , wherein the logic region includes a first region adjacent to the cell region and a second region adjacent to the first region.

3 . The method of claim 2 , wherein the removing removes the metal gate film in the first region and the at least a portion of the cell region, while the metal gate film remains in the second region.

4 . The method of claim 3 , wherein a gate electrode formed in the first region and a gate electrode formed in the second region have different widths.

5 . The method of claim 2 , wherein the removing removes the metal gate film in the at least a portion of the cell region, while the metal gate film remains in the first region and the second region.

6 . The method of claim 1 , wherein the forming a plurality of gate electrodes includes:
forming an erase gate electrode between the split gate structures; and forming a select gate electrode on an outside of each of the split gate structures.

7 . The method of claim 1 , wherein the removing comprises:
performing a wet-etching process in which the metal gate film is removed in at least a portion of the logic region and the cell region, the wet-etch process using an etching solution containing an SC 1 solution.

8 . The method of claim 1 , wherein the removing removes a portion of the metal gate film enclosing one end of the control gate electrode in an edge of the cell region.

9 . The method of claim 1 , wherein the first gate insulating film contains at least one of an aluminum oxide (Al 2 O 3 ), a tantalum oxide (Ta 2 O 3 ), a titanium oxide (TiO 2 ), an yttrium oxide (Y 2 O 3 ), a zirconium oxide (ZrO 2 ), a zirconium silicon oxide (ZrSi x O y ), a hafnium oxide (HfO 2 ), a hafnium silicon oxide (HfSi x O y ), a lanthanum oxide (La 2 O 3 ), a lanthanum aluminum oxide (LaAl x O y ), a lanthanum hafnium oxide (LaHf x O y ), a hafnium aluminum oxide (HfAl x O y ), and a praseodymium oxide (Pr 2 O 3 ).

10 . A method of manufacturing a semiconductor device, the method comprising:
forming split gates, each including a floating gate electrode and a control gate electrode in a cell region of a substrate, the substrate including the cell region and a logic region adjacent to the cell region; forming a first gate electrode layer such that an upper surface of the substrate is exposed in at least a portion of the logic region; sequentially forming a first gate insulating layer and a metal gate layer on the upper surface of the substrate exposed in the logic region; forming a second gate electrode layer on the logic region and the cell region; and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region by patterning the first and second gate electrode layers, the metal gate layer, and the first gate insulating layer.

11 . The method of claim 10 , wherein the logic region includes a first region and a second region, wherein the first region is disposed between the cell region and the second region.

12 . The method of claim 11 , wherein the forming of a first gate insulating layer and a metal gate layer comprises:
sequentially forming the first gate insulating layer and the metal gate layer in the second region.

13 . The method of claim 11 , wherein the forming of a first gate insulating layer and a metal gate layer comprises:
sequentially forming the first gate insulating layer and the metal gate layer in the first and second regions.

14 . The method of claim 10 , wherein the forming the plurality of memory cell elements comprises:
forming the first gate insulating layer and the metal gate layer in the logic region and the cell region; forming a mask layer exposing the cell region; and removing the metal gate layer from the cell region.

15 . A method of manufacturing a semiconductor device having a split gate structure, the method comprising:
forming a split gate structure on a substrate, the substrate including a cell region and a logic region; sequentially forming a first gate insulating film and a metal gate film on the split gate structures; removing a portion of the metal gate film; forming a second gate insulating film on the first gate insulating film; forming a gate electrode film on the cell region and the logic region; and forming an insulating layer, a first circuit element, a second circuit element, and a bit line on the substrate.

16 . The method of claim 15 , further comprising:
injecting an impurity in a partial region of the substrate between the split gate structures to form a first impurity region.

17 . The method of claim 16 , further comprising:
oxidizing the partial region of the substrate to form an oxide layer on the first impurity region.

18 . The method of claim 17 , wherein the oxide layer includes a central portion that is bulged.

19 . The method of claim 15 , wherein the removing a portion of the metal gate film completely removes the metal gate film in the cell region.

20 . The method of claim 15 , wherein the forming a split gate structure comprises:
forming a floating gate electrode and a control gate electrode in the cell region of the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Tea Kwang
• Kim Yong Tae
• Park Jae Hyun
• Yeom Kyong Sik

Classifications

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H01L27/11536 Primary

  Electricity · mapped topic

• H01L27/11541

  Electricity · mapped topic

• H10B41/30 Primary

  characterised by the memory core region · CPC title