Guard ring for memory array

Patent metadata

Field	Value
Publication number	US-9269766-B2
Application number	US-201414490629-A
Country	US
Kind code	B2
Filing date	Sep 18, 2014
Priority date	Sep 20, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.

First claim

What is claimed is:

1. A method for forming a device comprising:
providing a substrate having an array region in which memory cells are to be formed;
forming storage gates of the memory cells in the array region, wherein each of the storage gates comprises a floating gate and a control gate formed over the floating gate;
forming a guard ring surrounding the array region;
forming a gate electrode layer on the substrate, wherein the gate electrode layer fills gaps between the storage gates having the floating and control gates and guard ring as well as covering at least the control gates of the storage gates; and
planarizing the gate electrode layer to produce a planar surface between the gate electrode layer, storage gates and guard ring, wherein the guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.

2. The method of claim 1 wherein the guard ring is a storage gate guard ring which includes the same gate and dielectric layers as the storage gates of the memory cells.

3. The method of claim 1 wherein the guard ring is displaced away from the edge regions of the array region.

4. The method of claim 1 wherein the guard ring comprises a width which is uniform throughout all four sides of the guard ring.

5. The method of claim 1 wherein the guard ring comprises a width which is not uniform throughout all four sides of the guard ring.

6. The method of claim 5 wherein longer sides of the guard ring comprise a width dimension which is narrower than shorter sides of the guard ring.

7. The method of claim 1 wherein forming the storage gates comprises:
forming a floating gate dielectric layer on the substrate;
forming a floating gate electrode layer on the floating gate dielectric layer;
forming a control gate electrode layer; and
forming a storage dielectric layer in between the floating and control gate electrode layers.

8. The method of claim 7 comprising patterning the floating gate and storage dielectric layers as well as the floating and control gate electrode layers to simultaneously form the storage gates and the guard ring.

9. The method of claim 1 comprising:
forming first and second memory cell terminals adjacent to first and second sides of the storage gates, wherein the second memory cell terminals of adjacent storage gates form a common second cell terminal; and
wherein the gate electrode layer is recessed to a desired height to form at least access gates of the memory cells adjacent to the first memory cell terminals of the storage gates.

10. The method of claim 1 comprising:
forming first and second memory cell terminals adjacent to first and second sides of the storage gates, wherein the second memory cell terminals of adjacent storage gates form a common second cell terminal; and
wherein the gate electrode layer is recessed to a desired height to form access gates adjacent to the first memory cell terminals and erase gates over the common second cell terminals of the memory cells.

11. A method for forming a device comprising:
providing a substrate having an array region in which memory cells are to be formed;
forming storage gates of the memory cells in the array region, wherein each of the storage gates comprises a floating gate and a control gate formed over the floating gate and a storage dielectric layer formed in between the floating and control gates;
forming a guard ring surrounding the array region, wherein the guard ring is a storage gate guard ring which includes the same layers as the storage gates of the memory cells; and
forming a gate electrode layer on the substrate, wherein the gate electrode layer fills gaps between the storage gates having the floating and control gates and guard ring as well as covering at least the control gates of the storage gates.

12. The method of claim 11 wherein the guard ring comprises a height which is the same as height of the storage gates of the memory cells.

13. The method of claim 11 wherein forming the storage gates comprises:
forming a floating gate dielectric layer on the substrate;
forming a floating gate electrode layer on the floating gate dielectric layer;
forming a control gate electrode layer; and
forming a storage dielectric layer in between the floating and control gate electrode layers.

14. The method of claim 13 comprising patterning the floating gate and storage dielectric layers as well as the floating and control gate electrode layers to simultaneously form the storage gates and the guard ring.

15. The method of claim 11 comprising:
planarizing the gate electrode layer to produce a planar surface between the gate electrode layer, storage gates and guard ring, wherein the guard ring protects the gate electrode layer at edge region of the array region from being removed during planarizing the gate electrode layer.

16. The method of claim 15 comprising recessing the planarized gate electrode layer to a desired height to form access gates of the memory cells.

17. The method of claim 16 wherein the height of the access gates is controlled by controlling the height of the storage gates.

18. The method of claim 15 comprising recessing the planarized gate electrode layer to a desired height to form access gates and erase gates of the memory cells.

19. A method for forming a device comprising:
providing a substrate having an array region in which memory cells are to be formed and a logic region in which logic devices are to be formed;
forming storage gates of the memory cells in the array region, wherein each of the storage gates comprises a floating gate and a control gate formed over the floating gate and a storage dielectric layer formed in between the floating and control gates;
forming a guard ring surrounding the array region, wherein the guard ring is a storage gate guard ring which includes the same layers as the storage gates of the memory cells; and
forming a gate electrode layer on the substrate, wherein the gate electrode layer fills gaps between the storage gates having the floating and control gates and guard ring as well as covering at least the control gates of the storage gates and over the logic region.

20. The method of claim 19 comprising:
planarizing the gate electrode layer to produce a planar surface between the gate electrode layer, storage gates and guard ring in the array region and to produce a planar surface of the gate electrode layer in the logic region, wherein the guard ring protects the gate electrode layer at edge region of the array region from being removed during planarizing the gate electrode layer, and wherein the gate electrode layer in the logic region comprises a height which is lower than height of the gate electrode layer in the array region.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Wu Ling
• Yang Jianbo
• Lim Kian Hong
• Jung Sung Mun

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D62/106 Primary

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title