Three dimensional structures within mold compound

Patent metadata

Field	Value
Publication number	US-9711492-B2
Application number	US-201414778036-A
Country	US
Kind code	B2
Filing date	Dec 9, 2014
Priority date	Dec 9, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.

First claim

The invention claimed is:

1. A method comprising:
forming at least one passive structure on a substrate by a build-up process;
introducing one or more integrated circuit chips on the substrate;
introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips; and
after introducing the molding compound, the method comprises removing the substrate.

2. The method of claim 1 , wherein each of the at least one passive structure and the one or more integrated circuit chips comprise contact points and removing the substrate exposes the contact points, the method further comprising:
coupling a redistribution layer to the contact points.

3. A method comprising:
forming at least one passive structure on a substrate by a build-up process;
introducing one or more integrated circuit chips on the substrate; and
introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips,
wherein introducing the one or more chips comprises coupling contact points of the one or more chips to contact points of the substrate, and
wherein the build-up process comprises repeatedly depositing a layer of conductive powder on the substrate and selectively melting the conductive powder in the deposited layer or the build-up process comprises stereo lithography.

4. The method of claim 3 , wherein the one or more chips are coupled to the substrate through solder connections.

5. The method of claim 3 , wherein forming the at least one passive structure on the substrate comprises coupling the at least one passive structure to respective one or more contact points of the substrate.

6. The method of claim 1 , wherein the at least one passive structure comprises a coil.

7. The method of claim 1 , wherein the at least one passive structure comprises at least one of an antenna, a resistor or a shield.

8. A package substrate is made by the method of claim 1 .

9. A method comprising:
forming at least one passive structure on a substrate by a three-dimensional printing process;
introducing one or more integrated circuit chips on the substrate;
embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound; and
after embedding the at least one passive structure and the one or more integrated circuits in the molding compound, the method comprises removing the substrate.

10. The method of claim 9 , wherein each of the at least one passive structure and the one or more integrated circuit chips comprise contact points and removing the substrate exposes the contact points, the method further comprising:
coupling a metallization layer to the contact points.

11. A method comprising:
forming at least one passive structure on a substrate by a three-dimensional printing process;
introducing one or more integrated circuit chips on the substrate; and

embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound,
wherein introducing the one or more chips comprises coupling contact points of the one or more chips to contact points of the substrate, and
wherein the three-dimensional printing process comprises repeatedly depositing a layer of conductive powder on the substrate and selectively melting the conductive powder in the deposited layer or comprises stereo lithography.

12. The method of claim 11 , wherein the one or more chips are coupled to the substrate through solder connections.

13. The method of claim 11 , wherein forming the at least one passive structure on the substrate comprises coupling the at least one passive structure to respective one or more contact points of the substrate.

14. A package substrate is made by the method of claim 9 .

15. An apparatus comprising:
a package substrate comprising at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material, wherein the package substrate includes first contact points on a first side and second contact points on an opposite second side and wherein the one or integrated circuit chips are coupled to ones of the first contact points.

16. The apparatus of claim 15 , wherein the at least one passive structure comprises at least one of an antenna, a resistor, a coil or a shield.

17. The apparatus of claim 15 , wherein the at least one passive structure is coupled to other ones of the first contact points of the package substrate.

18. The apparatus of claim 15 , wherein the one or more integrated circuit chips are coupled to ones of the first contact points of the substrate through solder connections.

19. The method of claim 3 , wherein the at least one passive structure comprises a coil.

20. The method of claim 3 , wherein the at least one passive structure comprises at least one of an antenna, a resistor or a shield.

Assignees

• Intel Corp

Inventors

• Albers Sven
• Wolter Andreas
• Reingruber Klaus
• Meyer Thorsten

Classifications

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title