Three-dimensional passive components

US2016172099A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016172099-A1
Application numberUS-201514964451-A
CountryUS
Kind codeA1
Filing dateDec 9, 2015
Priority dateDec 10, 2014
Publication dateJun 16, 2016
Grant date

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Abstract

Official abstract text for this publication.

Three-dimensional inductors may comprise a passivation layer disposed on a substrate, a three-dimensional pillar comprising a ferromagnetic material disposed on the substrate or the passivation layer, and a conductive trace wound at least partially around the pillar. Three-dimensional capacitors may comprise a passivation layer disposed on a substrate, at least two support pillars comprising a polymeric material disposed on the passivation layer or the substrate, at least two electrodes disposed between the support pillars, a dielectric disposed between the electrodes, and a metal trace. Methods of manufacturing the three-dimensional passives, such as inductors and capacitors, may comprise direct writing the components and curing them for on-chip applications.

First claim

Opening claim text (preview).

What is claimed is: 1 . A device comprising: a substrate; a pillar disposed on at least a portion of the substrate layer, the pillar comprising a ferromagnetic material or a polymer, the pillar defining a three-dimensional structure projecting out from the substrate; and a conductive trace wound at least partially around the pillar. 2 . The device of claim 1 , wherein the ferromagnetic material comprises iron, barium titanate, germanium telluride, polyvinylidene fluoride, or a combination thereof, and the polymer comprises acrylate urethane 3 . The device of claim 1 , wherein the conductive trace comprises sintered silver, cupric oxide, copper, platinum, gold, aluminum, a conducting polymer, or a combination thereof. 4 . The device of claim 1 , wherein the pillar projects out from the substrate between approximately 1 μm and approximately 1 mm. 5 . The device of claim 1 , further comprising: a passivation layer disposed between the substrate and the pillar. 6 . The device of claim 1 , wherein the pillar abuts a surface of the passivation layer. 7 . A device comprising: a silicon chip; two support pillars disposed on at least a portion of the silicon chip, the two support pillars comprising a polymeric material; two electrodes disposed between the two support pillars; a dielectric disposed at least partially between the two electrodes and in contact with the two electrodes; and a conductive trace in contact with the two support pillars, the two electrodes, and the dielectric. 8 . The device of claim 7 , wherein the dielectric comprises barium titanate, a polymer, a composite of barium titanate and the polymer, or air. 9 . The device of claim 7 , further comprising: a passivation layer disposed between the two support pillars and the substrate. 10 . The device of claim 9 , wherein the three-dimensional capacitor projects out from the substrate between approximately 1 μm and approximately 1 mm. 11 . The device of claim 7 , wherein the two support pillars comprise a conductive material and serve as the two electrodes. 12 . A method of manufacturing a three-dimensional inductor, comprising: direct writing a three-dimensional pillar, comprising a nanoparticle ink or a polymer containing nanoparticles, onto a surface of a substrate or a passivation layer disposed on the surface of the substrate; hardening and sintering the nanoparticle ink; curing the polymer; direct writing a conductive trace, comprising a metal nanoparticle ink or a conductive polymer, around at least a portion of the three-dimensional pillar; direct writing an insulation layer disposed proximate to the three-dimensional pillar; further direct writing a portion of the conductive trace onto the insulation layer such that the portion of the conductive trace on the insulation layer does not contact the conductive trace around the at least the portion of the three-dimensional pillar; and sintering the metal nanoparticle ink. 13 . The method of claim 12 , wherein direct writing the conductive trace further comprises: synchronizing movement of a dispenser of the metal nanoparticle ink or the conductive polymer and rotation of a base holding the substrate such that the metal trace winds around the three-dimensional pillar to form a coil. 14 . The method of claim 12 , wherein the nanoparticle ink comprises iron, barium titanate, germanium telluride, polyvinylidene fluoride, or a combination thereof. 15 . The method of claim 12 , wherein the metal nanoparticle ink comprises silver, cupric oxide, copper, platinum, gold, aluminum, or a combination thereof. 16 . The method of claim 12 , wherein the direct writing of the three-dimensional pillar and the direct writing of the metal trace is performed by three-dimensional printing. 17 . A method of manufacturing a three-dimensional capacitor, comprising: direct writing a first three-dimensional support pillar, comprising a polymer, onto a surface of a substrate or a passivation layer disposed on the surface of the substrate; direct writing a first electrode onto a surface of the first three-dimensional support pillar; supplying a dielectric, comprising a nanoparticle ink or air, onto a surface of the first electrode; direct writing a second three-dimensional support pillar, comprising the polymer, onto the passivation layer or the substrate; direct writing a second electrode onto a surface of the second three-dimensional support pillar; and direct writing a conductive trace, comprising a metal nanoparticle ink or a conductive polymer, onto the first three-dimensional support pillar, the second three-dimensional support pillar, the first electrode, the second electrode, and the dielectric. 18 . The method of claim 17 , wherein the first three-dimensional support pillar and the second three-dimensional support pillar comprise a conductive material and serve as the first electrode and the second electrode. 19 . The method of claim 17 , wherein the dielectric provides for dielectric polarization creating an electric field within a least a portion of the dielectric. 20 . The method of claim 19 , further comprising: direct writing additional electrodes between the first three-dimensional support pillar and the second three-dimensional support pillar; direct writing additional dielectric material such that the additional dielectric material is in contact with the additional electrodes and such that the additional electrodes are not in contact with each other or with the two electrodes; and direct writing additional conductive traces to electronically couple the additional electrodes to the two electrodes.

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What does patent US2016172099A1 cover?
Three-dimensional inductors may comprise a passivation layer disposed on a substrate, a three-dimensional pillar comprising a ferromagnetic material disposed on the substrate or the passivation layer, and a conductive trace wound at least partially around the pillar. Three-dimensional capacitors may comprise a passivation layer disposed on a substrate, at least two support pillars comprising a …
Who is the assignee on this patent?
Univ Washington State
What technology area does this patent fall under?
Primary CPC classification B22F10/10. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Thu Jun 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).