Multi-chip fan out package and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9691706-B2
Application number	US-201213452140-A
Country	US
Kind code	B2
Filing date	Apr 20, 2012
Priority date	Jan 23, 2012
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

First claim

What is claimed is:

1. A device comprising:
a first die comprising:
a conductive pad at a top surface of the first die and a semiconductor substrate underlying the conductive pad;
a first stud bump over and connected to the conductive pad, wherein the first stud bump is a wire bonding stud bump having non-vertical sidewalls and a first planar top surface; and
a dielectric layer, wherein the first stud bump is in the dielectric layer, and edges of the dielectric layer are coplanar with respective edges of the semiconductor substrate, wherein a top surface of the dielectric layer is coplanar with the first planar top surface of the first stud bump;

a second die comprising:
active devices; and
a second stud bump electrically coupled to the active devices, wherein the second stud bump is a wire bonding stud bump having non-vertical sidewalls;

a polymer encircling the first die and contacting sidewalls of the first die, wherein the dielectric layer and the polymer comprise different materials, and the polymer comprises a portion directly over a portion of the second die and in physical contact with the second stud bump;
a redistribution line over and contacting the first stud bump; and
an electrical connector over and electrically coupled to the redistribution line.

2. The device of claim 1 , wherein a bottom surface of the polymer is substantially level with a bottom surface of the first die.

3. The device of claim 1 , wherein a top surface of the polymer is level with the first planar top surface of the first stud bump.

4. A device comprising:
a first die comprising:
a semiconductor substrate;
a first conductive pad at a top surface of the first die; and
a first stud bump over and connected to the first conductive pad, wherein the first stud bump is a wire bonding stud bump having non-vertical sidewalls and a first planar top surface;

a polymer encircling the first die and contacting sidewalls of the first die, wherein a bottom surface of the polymer is substantially level with a bottom surface of the semiconductor substrate, and a top surface of the polymer is substantially level with the first planar top surface of the first stud bump; and
a first redistribution line over and contacting the first stud bump; and
a dielectric layer, wherein the first stud bump is in the dielectric layer, and the first stud bump is spaced apart from the polymer by the dielectric layer, wherein the dielectric layer and the polymer comprise different materials, and wherein edges of the dielectric layer are perpendicular to the bottom surface of the polymer, and a top surface of the dielectric layer is coplanar with the first planar top surface of the stud bump;
a second die encircled by the polymer, wherein the second die comprises:
a second substrate;
active devices at a surface of the second substrate;
a second conductive pad at a top surface of the second die; and
a second stud bump over and connected to the second conductive pad, wherein the polymer comprises a portion overlapping the second die, and wherein the portion of the polymer encircles and physically contacts the second stud bump.

5. The device of claim 4 , wherein the edges of the dielectric layer are coplanar with respective edges of the semiconductor substrate.

6. The device of claim 4 , wherein the top surface of the polymer is substantially level with a top surface of the second stud bump.

7. The device of claim 4 , wherein the polymer comprises a portion disposed into a space between the first die and the second die, and wherein the first redistribution line overlaps the portion of the polymer.

8. A device comprising:
a first die comprising:
a conductive pad at a top surface of the first die;
a first stud bump comprising:
a bump portion with a non-flat top surface, wherein a bottom surface of the bump portion is in physical contact with a top surface of the conductive pad; and
a wire portion over and connected to the bump portion, wherein the wire portion and the bump portion are formed of a same material, and are connected to each other integrally, and the wire portion has a first planar top surface;
a first dielectric layer encircling and in physical contact with both the bump portion and the wire portion of the first stud bump, with a top surface of the first dielectric layer being coplanar with a top surface of the wire portion;

a molding compound encircling and contacting edges of the first die, with a top surface of the molding compound being coplanar with a top surface of the wire portion;
a second dielectric layer over a top surface of the first die and over and contacting the top surface of the molding compound;
a redistribution line in the second dielectric layer and contacting the top surface of the wire portion;
a solder region over and electrically coupled to the redistribution line; and
a second die comprising active circuits and a second stud bump, wherein the second stud bump is a wire bonding stud bump having non-vertical sidewalls, wherein the molding compound is in physical contact with the second stud bump, wherein the second stud bump has a second planar top surface coplanar with both the first planar top surface and the top surface of the molding compound, and wherein a back surface of the first die and a back surface of the second die are both coplanar with a surface of the molding compound.

9. The device of claim 8 , wherein the conductive pad and the first stud bump are formed of different materials.

10. The device of claim 8 , wherein the bump portion is wider than the wire portion.

11. The device of claim 8 , wherein the molding compound is in physical contact with the second stud bump.

12. The device of claim 8 , wherein the first die further comprises a semiconductor substrate, and edges of the first dielectric layer are co-terminus with edges of the semiconductor substrate.

13. The device of claim 2 , wherein the bottom surface of the polymer is coplanar with a bottom surface of the semiconductor substrate.

14. The device of claim 1 , wherein the dielectric layer comprises polybenzoxazole (PBO) or benzocyclobutene (BCB).

15. The device of claim 8 , wherein the first dielectric layer comprises polybenzoxazole (PBO).

16. The device of claim 8 , wherein the first dielectric layer comprises benzocyclobutene (BCB).

17. The device of claim 1 , wherein the second stud bump has a second planar top surface coplanar with both the first planar top surface and the top surface of the polymer, and wherein a back surface of the first die and a back surface of the second die are both coplanar with a bottom surface of the polymer.

18. The device of claim 4 , wherein the second stud bump has a second planar top surface coplanar with both the first planar top surface and the top surface of the polymer, and wherein a bottom surface of the second die is coplanar with the bottom surface of the polymer.

Assignees

• Yu Chen-Hua
• Lin Jing-Cheng
• Hung Jui-Pin
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Lin Jing-Cheng
• Hung Jui-Pin

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W46/301

  for alignment · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/0112

  Apparatus for manufacturing bump connectors · CPC title