Semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9665448-B2
Application number	US-201414461935-A
Country	US
Kind code	B2
Filing date	Aug 18, 2014
Priority date	Mar 8, 2010
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A semiconductor integrated circuit pertaining to the present invention comprises a plurality of storage elements for storing and holding an input signal, a majority circuit that outputs a result of a majority decision of outputs from the plurality of storage elements; an error detector circuit that detects a mismatch among the outputs of the plurality of storage elements and outputs error signals; and a monitor circuit that monitors the error signals from the error detector circuit, wherein the monitor circuit, based on the error signals, orders a refresh action that rewrites data for rectification to a storage element in which an output mismatch occurs out of the plurality of storage elements and, if rewrite and rectification by the refresh action are unsuccessful, sends a notification to an external unit or process.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a first, a second and a third memory in synchronization with a clock;
a majority unit that receives a first, a second and a third value from the first, second and third memories respectively, and outputs a result of a majority vote of the first, the second and the third value; and
an error detector that receives the first, the second and the third value, from the first, second and third memories respectively, that detects a mismatch between any one of the first, second and third values and both of the others of the first, second and third values, and that outputs an error signal indicating the one of the first, second and third values which is different from both of the others of the first, second and third values,
wherein the value causing the mismatch, detected by the error detector, among the first, second and third values is replaced by the result of the majority vote output by the majority unit when the mismatch is detected by the error detector,
wherein the replacement is executed by supplying the result of the majority vote and the clock to the memory causing the mismatch among the first, second and third memories.

2. The semiconductor integrated circuit according to claim 1 , wherein the semiconductor integrated circuit outputs a notification when the mismatch is still detected after the replacement.

3. The semiconductor integrated circuit according to claim 1 , further comprising a central processing unit (CPU),
wherein the replacement is executed independently from the CPU.

4. A method of a majority vote by a semiconductor integrated circuit (IC), the method comprising the steps of:
(a) receiving into a majority unit of the IC, a first, a second and a third value from a first, a second and a third memory, respectively, which are in synchronization with a clock, and generating via the majority unit a result of a majority vote of the first, the second and the third value;
(b) receiving into an error detector of the IC the first, the second and the third value, from the first, second and third memories respectively, detecting via the error detector a mismatch between any one of the first, second and third values and both of the others of the first, second and third values by the error detector, and outputting via the error detector an error signal indicating the one of the first, second and third values which is different from both of the others of the first, second and third values; and
(c) replacing the value causing the detected mismatch among the first, second and third values with the result of the majority vote output by the majority unit when the mismatch is detected by the error detector,
wherein the replacement is executed by supplying the result of the majority vote to the memory causing the mismatch among the first, second and third memories.

5. The method according to claim 4 , further comprising:
(d) indicating a notification by the IC when the mismatch is still detected after the replacing.

Assignees

• Renesas Electronics Corp

Inventors

• Nakamura Koichi

Classifications

• H03M13/05

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/183 Primary

  by voting, the voting not being performed by the redundant components · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• H03K19/007 Primary

  Fail-safe circuits · CPC title