Microcontroller utilizing redundant address decoders and electronic control device using the same

Patent metadata

Field	Value
Publication number	US-9811429-B2
Application number	US-201514705127-A
Country	US
Kind code	B2
Filing date	May 6, 2015
Priority date	May 22, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.

First claim

What is claimed is:

1. A microcontroller comprising three or more processors and a storage device,
wherein the three or more processors are configured to execute a same process in parallel,
wherein the storage device includes a non-redundant memory mat having storage regions each corresponding to an address issued at a time of an access by a processor, an address selection part selecting a storage region in the memory mat on a basis of three or more addresses issued at a time of an access by the three or more processors, a data output part reading data from the storage region in the memory mat selected by the address selection part, and a failure recovery part correcting or masking a detected failure which occurs in the memory mat, the address selection part, or the data output part, and
wherein the address selection part comprises a plurality of address decoders and a majority logic circuit which selects the selected storage region by a result of majority vote of outputs of the plurality of address decoders.

2. The microcontroller according to claim 1 ,
wherein the memory mat comprises L words each corresponding to one of the storage regions and each made of W bits (W and L are natural numbers),
wherein the plurality of address decoders each output to the majority logic circuit a selection signal selecting one word from the L words on a basis of an address supplied, and
wherein the majority logic circuit selects one word from the L words of the memory mat as the selected storage region.

3. The microcontroller according to claim 2 , wherein the failure recovery part performs 1-bit error correction 2-bit error detection on data read from the memory mat.

4. The microcontroller according to claim 2 ,
wherein the microcontroller has first, second, and third processors as the three or more processors,
wherein the first, second, and third processors issue first, second, and third addresses, respectively, to access the storage device,
wherein the microcontroller further comprises a first comparator comparing the first and second addresses, a second comparator comparing the second and third addresses, and a plurality of selectors to which the first and third addresses are supplied and which supplies, on a basis of a comparison result of the first and second comparators, any one of the first and third addresses to a corresponding address decoder, and
wherein each of the plurality of selectors is a circuit which supplies the first address to a corresponding address decoder when a comparison result of the first comparator indicates that the first and second addresses are equal to each other, and which supplies the third address to a corresponding address decoder when a comparison result of the first comparator indicates that the first and second addresses are not equal to each other and a comparison result of the second comparator indicates that the second and third addresses are equal to each other.

5. The microcontroller according to claim 2 ,
wherein the microcontroller has first, second, third, and fourth processors as the three or more processors,
wherein the first, second, third, and fourth processors issue first, second, third, and fourth addresses, respectively, to access the storage device,
wherein the microcontroller further comprises a first comparator comparing the first and second addresses, a second comparator comparing the third and fourth addresses, and a plurality of selectors to which the first and third addresses are supplied and which supplies, on a basis of a comparison result of the first and second comparators, any one of the first and third addresses to a corresponding address decoder, and
wherein each of the plurality of selectors is a circuit which supplies the first address to a corresponding address decoder when a comparison result of the first comparator indicates that the first and second addresses are equal to each other, and which supplies the third address to a corresponding address decoder when a comparison result of the first comparator indicates that the first and second addresses are not equal to each other and a comparison result of the second comparator indicates that the third and fourth addresses are equal to each other.

6. The microcontroller according to claim 2 ,
wherein each of the plurality of address decoders has a row decoder and a column decoder.

7. The microcontroller according to claim 1 ,
wherein the three or more processors and the storage device are configured on a single semiconductor substrate.

8. An electronic control device on which the microcontroller described in claim 1 is mounted.

9. The microcontroller according to claim 1 ,
wherein the address selection part comprises a plurality of redundant address decoders each outputting a selection signal selecting a storage region on a basis of an address supplied.

10. A microcontroller comprising three or more processors and a storage device,
wherein the three or more processors are configured to execute a same process in parallel,
wherein the storage device includes a non-redundant memory mat having storage regions each corresponding to an address issued at a time of an access by a processor, an address selection part selecting a storage region in the memory mat on a basis of three or more addresses issued at a time of an access by the three or more processors, a data output part reading data from the storage region in the memory mat selected by the address selection part, and a failure recovery part correcting or masking a detected failure which occurs in the memory mat, the address selection part, or the data output part,
wherein the failure recovery part is configured to execute an error correction on a code word of c symbols of a Reed-Solomon code using b bits as one symbol, on data read from the memory mat (b and c are natural numbers),
wherein the memory mat comprises L words each corresponding to one of the storage regions, each made of W bits (W and L are natural numbers) and each divided into a plurality of partial memory mats of L words each made of b bits or less,
wherein the address selection part comprises a plurality of address decoders each outputting a selection signal selecting one word from the L words on a basis of an address supplied and each associated with a respective one of the plurality of partial memory mats,
wherein a number of the plurality of partial memory mats is a plural number less than or equal to c, and
wherein a number of the plurality of address decoders is equal to the number of the plurality of partial memory mats.

11. The microcontroller according to claim 10 ,
wherein the failure recovery part executes the error correction by adding at least one bit of known value to data read from the partial memory mat when the number of bits per word is less than the b bits in each word of the plurality of partial memory mats, and
wherein the failure recovery part executes the error correction by adding a known bit string to data read from the plurality of partial memory mats when the number of the plurality of partial memory mats is less than c.

12. The microcontroller according to claim 10 ,
wherein the failure recovery part is configured to execute an error correction on data read from the memory mat using a code word of 10 symbols of a Reed-Solomon code and four bits as one symbol,
wherein the L words are each made of 32 bits and are divided into 10 partial memory mats of L words each made of four bits, and
wherein the address selection part comprises a plurality of address decoders each outputting a selection signal selecting one word from the L words on a basis of an address supplied and each associated with a respect

Assignees

• Renesas Electronics Corp

Inventors

• Kanekawa Nobuyasu
• Arimitsu Hitoshi
• Yasumasu Takashi
• Matsuyama Hideki

Classifications

• G06F11/183

  by voting, the voting not being performed by the redundant components · CPC title

• G05B19/042 Primary

  using digital processors (G05B19/05 takes precedence) · CPC title

• G06F11/187

  Voting techniques · CPC title

• G06F2201/85

  Active fault masking without idle spares · CPC title

• G06F11/1641

  where the comparison is not performed by the redundant processing components · CPC title