Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it

Patent metadata

Field	Value
Publication number	US-9577960-B2
Application number	US-201414581570-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 27, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I 0 , I 1 . . . , I 2k-1 , and I 2k , digital output signals of the error-correction unit with fault-tolerant nature are separately O 0 , O 1 , . . . , O k-2 , and O k-1 , and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O 0 =I 0 if I 0 =I 1 , and O 0 =I 2 otherwise; and when k>1, set O k-1 =I 2k-1 if O k-2 =I 2k-1 , and O k-1 =I 2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.

First claim

What is claimed is:

1. A universal error-correction circuit with fault-tolerant nature, comprising:
an error-correction unit with fault-tolerant nature implemented by a logic gate,
wherein digital input signals of the error-correction unit with fault-tolerant nature are separately I 0 , I 1 . . . , I 2k-1 , and I 2k ,
wherein a number of the digital input signals that exist in the universal error-correction circuit with fault-tolerant nature is 2k+1,
wherein digital output signals of the error-correction unit with fault-tolerant nature are separately O 0 , O 1 . . . , O k-2 , and O k-1 ,
wherein a number of the digital output signals that exist in the universal error-correction circuit with fault-tolerant nature is k,
wherein the digital input signals and the digital output signals belong to a set {0,1},
wherein k is a positive integer,
wherein the error-correction unit with fault-tolerant nature is configured to:
set O 0 =I 0 when k=1 and I 0 =I 1 ;
set O 0 =I 2 when I 0 is not equal to I 1 ;
set O k-1 =I 2k-1 when k>1 and O k-2 =I 2k-1 ; and
set O k-1 =I 2k when O k-1 is not equal to I 2k-1 ,

wherein when k=3 in the error-correction unit with fault-tolerant nature, seven corresponding digital input signals are separately I 0 , I 1 , I 2 , I 3 , I 4 , I 5 , and I 6 , and three corresponding digital output signals are separately O 0 , O 1 , and O 2 ,
wherein the error-correction unit with fault-tolerant nature comprises three error-correction subunits with fault-tolerant nature, which are separately a first error-correction subunit with fault-tolerant nature, a second error-correction subunit with fault-tolerant nature, and a third error-correction subunit with fault-tolerant nature, each error-correction subunit with fault-tolerant nature is corresponding to three digital input signals and one digital output signal, and each error-correction subunit with fault-tolerant nature comprises a first AND gate, a first OR gate, a second AND gate, and a second OR gate,
wherein two input signals of both the first AND gate and the first OR gate are a first digital input signal and a second digital input signal, one input signal of the second AND gate is a third digital input signal, the other input signal of the second AND gate is an output signal of the first OR gate, and an output signal of the second AND gate and an output signal of the first AND gate serve as two input signals of the second OR gate,
wherein a first digital input signal, a second digital input signal, and a third digital input signal of the first error-correction subunit with fault-tolerant nature are I 0 , I 1 , and I 2 , respectively, and an output signal of the first error-correction subunit with fault-tolerant nature is O 0 ,
wherein a first digital input signal, a second digital input signal, and a third digital input signal of the second error-correction subunit with fault-tolerant nature are I 3 , I 4 , and O 0 , respectively, and an output signal of the second error-correction subunit with fault-tolerant nature is O 1 , and
wherein a first digital input signal, a second digital input signal, and a third digital input signal of the third error-correction subunit with fault-tolerant nature are I 5 , I 6 , and O 1 , respectively, and an output signal of the third error-correction subunit with fault-tolerant nature is O 2 .

2. The universal error-correction circuit with fault-tolerant nature according to claim 1 , wherein the universal error-correction circuit with fault-tolerant nature comprises a universal decoder.

3. The universal error-correction circuit with fault-tolerant nature according to claim 2 , wherein the universal decoder comprises a variable node circuit, an interleaver, a check node circuit, and a de-interleaver.

4. The universal error-correction circuit with fault-tolerant nature according to claim 3 , wherein the variable node circuit comprises the universal error-correction circuit with fault-tolerant nature.

5. The universal error-correction circuit with fault-tolerant nature according to claim 3 , wherein the interleaver is configured to randomly shuffle a received information sequence, read the randomly shuffled information sequence from front to back, and send the read information sequence to the check node circuit.

6. The universal error-correction circuit with fault-tolerant nature according to claim 3 , wherein the check node circuit is configured to calculate external information output by the variable node circuit to obtain an information value of a check node.

7. The universal error-correction circuit with fault-tolerant nature according to claim 3 , wherein the check node circuit comprises an exclusive-OR gate circuit.

8. The universal error-correction circuit with fault-tolerant nature according to claim 3 , wherein the de-interleaver is configured to randomly shuffle an information sequence and arrange the randomly shuffled information sequence from back to front.

9. A universal error-correction circuit with fault-tolerant nature, comprising:
an error-correction unit with fault-tolerant nature implemented by a logic gate,
wherein digital input signals of the error-correction unit with fault-tolerant nature are separately I 0 , I 1 . . . , I 2k-1 , and I 2k ,
wherein digital output signals of the error-correction unit with fault-tolerant nature are separately O 0 , O 1 . . . , O k-2 , and I k-1 ,
wherein the digital input signals and the digital output signals belong to a set {0,1},
wherein k is a positive integer, and
wherein the error-correction unit with fault-tolerant nature is configured to:
set O 0 =I 0 when k=1 and I 0 =I 1 ;
set O 0 =I 2 when I 0 is not equal to I 1 ;
set O k-1 =I 2k-1 when k>1 and O k-2 =I 2k-1 ; and
set O k-1 =I 2k when O k-1 is not equal to I 2k-1 ,

wherein when k=3 in the error-correction unit with fault-tolerant nature, seven corresponding digital input signals are separately I 0 , I 1 , I 2 , I 3 , I 4 , I 5 , and I 6 , and three corresponding digital output signals are separately O 0 , O 1 , and O 2 ,
wherein the error-correction unit with fault-tolerant nature comprises three error-correction subunits with fault-tolerant nature, which are separately a first error-correction subunit with fault-tolerant nature, a second error-correction subunit with fault-tolerant nature, and a third error-correction subunit with fault-tolerant nature, each error-correction subunit with fault-tolerant nature is corresponding to three digital input signals and one digital output signal, and each error-correction subunit with fault-tolerant nature comprises a first AND gate, a first OR gate, a second AND gate, and a second OR gate,
wherein two input signals of both the first AND gate and the first OR gate are a first digital input signal and a second digital input signal, one input signal of the second AND gate is a third digital input signal, the other input signal of the second AND gate is an output signal of the first OR gate, and an output signal of the second AND gate and an output signal of the first AND gate serve as two input signals of the second OR gate,
wherein a first digital input signal, a second digital input signal, and a third digital input signal of the first error-correction subunit with fault-tolerant nature are I 0 , I 1 , and I 2 , respectively, and an output signal of the first error-correction subunit with fault-tolerant nature is O 0 ,
wherein a first digital input signal, a second digital input signal, and a third digital input signal of the second error-correction subunit with fault-tolerant nature are I 3 , I 4 , and O 0 , respectively, and an output signal of the second error-correction subunit with fault-tolerant nature is O 1 , and
wherein a first d

Assignees

• Huawei Tech Co Ltd

Inventors

• Tang Yangyang
• Zhang Chen-Xiong

Classifications

• H04L49/557 Primary

  Error correction, e.g. fault recovery or fault tolerance · CPC title

• H03K19/23

  Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs · CPC title

• H03M13/43

  Majority logic or threshold decoding · CPC title

• G06F11/187 Primary

  Voting techniques · CPC title

• H03M13/1105

  Decoding · CPC title