Recoverable and fault-tolerant CPU core and control method thereof

Patent metadata

Field	Value
Publication number	US-9529654-B2
Application number	US-201414547301-A
Country	US
Kind code	B2
Filing date	Nov 19, 2014
Priority date	Nov 27, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.

First claim

What is claimed is:

1. A recoverable and fault-tolerant central processing unit (CPU) core, comprising:
first, second, and third arithmetic logic circuits configured to perform a calculation requested by a same instruction;
a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state;
a register file configured to record a calculation value having the same value, when determining as the normal state in the first selector, and
a second selector configured to compare control signals output from the first, second, and third arithmetic logic circuits, determine as a normal state when two or more of the control signals are the same, and if not, determine as a fault state, the control signal designating a same address to be read in the register file.

2. The recoverable and fault-tolerant CPU core of claim 1 , wherein the first selector is connected to the register file through an update bus.

3. The recoverable and fault-tolerant CPU core of claim 1 , further comprising a fault controller configured to control an operation of the first, second, and third arithmetic logic circuits when determining as the fault state in the first selector.

4. The recoverable and fault-tolerant CPU core of claim 3 , wherein each of the first, second, and third arithmetic logic circuits comprises a program counter controller configured to store a program counter value generated by executing until a current clock cycle in the first, second, and third arithmetic logic circuits when receiving a fault signal indicating the fault state from the fault controller.

5. The recoverable and fault-tolerant CPU core of claim 4 , wherein the program counter controller terminates an execution of an instruction after the program counter value in a pipeline structure in front of an execution unit which is included in each of the first, second, and third arithmetic logic circuits.

6. The recoverable and fault-tolerant CPU core of claim 4 , wherein the program counter controller provides the program counter value to an instruction access unit which is included in each of the first, second, and third arithmetic logic circuits, and controls the instruction access unit to read an instruction again from the program counter value when a fault is generated.

7. The recoverable and fault-tolerant CPU core of claim 1 , wherein each of the first, second, and third arithmetic logic circuits reads a register value from the register file according to the control signal having the same value when determining as the normal state in the second selector.

8. The recoverable and fault-tolerant CPU core of claim 1 , further comprising a fault controller configured to control an operation of the first, second, and third arithmetic logic circuits when determining as the fault state in the second selector, and
wherein each of the first, second, and third arithmetic logic circuits comprises a program counter controller configured to store a program counter value generated by executing until a current clock cycle in the first, second, and third arithmetic logic circuits when receiving a fault signal indicating the fault state in the second selector from the fault controller.

9. The recoverable and fault-tolerant CPU core of claim 8 , wherein the program counter controller terminates an execution of an instruction after the program counter value in a pipeline structure in front of an execution unit which is included in each of the first, second, and third arithmetic logic circuits.

10. The recoverable and fault-tolerant CPU core of claim 8 , wherein the program counter controller provides the program counter value to an instruction access unit which is included in the first, second, and third arithmetic logic circuits, and controls the instruction access unit to read an instruction again from the program counter value when a fault is generated.

11. A control method of a central processing unit (CPU) core comprising first, second, and third arithmetic logic circuits, a register file, and a first selector configured to compare calculation values output by a same instruction from the first, second, and third arithmetic logic circuits, comprising:
comparing the calculation values output by the same instruction from the first, second, and third arithmetic logic circuits, determining as a normal state when two or more of the calculation values are the same, and if not, determining as a fault state;
recording a calculation value having the same value in the register file, when determining as the normal state, and
controlling an operation of the first, second, and third arithmetic logic circuits when determining as the fault state,
wherein the controlling of the operation comprises:
storing a program counter value generated by executing until a current clock cycle in the first, second, and third arithmetic logic circuits;
terminating an execution of an instruction after the program counter value in a pipeline structure in front of an execution unit which is included in each of the first, second, and third arithmetic logic circuits; and
providing the program counter value to an instruction access unit which is included in the first, second, and third arithmetic logic circuits, and controlling the instruction access unit to read an instruction again from the program counter value when a fault is generated.

12. A control method of a central processing unit (CPU) core comprising first, second, and third arithmetic logic circuits, a register file, and a second selector configured to compare control signals output from the first, second, and third arithmetic logic circuits, comprising:
comparing the control signals output from the first, second, and third arithmetic logic circuits, determining as a normal state when two or more of the control signals are the same, and if not, determining as a fault state; and
reading a register value from the register file according to a control signal having the same value in the register file, when determining as the normal state.

13. The control method of claim 12 , further comprising:
controlling an operation of the first, second, and third arithmetic logic circuits when determining as the fault state, and
wherein the controlling of the operation comprises:
storing a program counter value generated by executing until a current clock cycle in the first, second, and third arithmetic logic circuits;
terminating an execution of an instruction after the program counter value in a pipeline structure in front of an execution unit which is included in each of the first, second, and third arithmetic logic circuits; and
providing the program counter value to an instruction access unit which is included in the first, second, and third arithmetic logic circuits, and controlling the instruction access unit to read an instruction again from the program counter value when a fault is generated.

14. The control method of claim 12 , wherein the control signal designates a same address to be read in the register file.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Kwon Young Su
• Han Jin Ho
• Byun Kyung Jin

Classifications

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/183

  by voting, the voting not being performed by the redundant components · CPC title

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title