Diluted drift layer with variable stripe widths for power transistors

Patent metadata

Field	Value
Publication number	US-9653577-B2
Application number	US-201615220910-A
Country	US
Kind code	B2
Filing date	Jul 27, 2016
Priority date	Mar 27, 2015
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

First claim

The invention claimed is:

1. A method of forming a lateral power MOS transistor, comprising
providing a substrate doped with a first dopant type having a well thereon doped a second dopant type with a semiconductor surface doped said second dopant type on said well;
forming dielectric isolation regions at least partially in said semiconductor surface having gaps defining a first active area in a first dielectric gap region (first MOAT) and a second active area in a second dielectric gap region (second MOAT);
forming a buried drift layer (BDL) doped said first dopant type having a diluted BDL portion (DBDL) including a plurality of dilution stripes, comprising:
forming a masking pattern using a diluted BDL mask having said plurality of dilution stripes with respective stripe widths that increase monotonically with a drift length at their respective positions, and
implanting using said masking pattern;

forming a drain comprising a plurality of drain fingers having drain fingertips in said second MOAT interdigitated with a source comprising a plurality of source fingers having source fingertips in said first MOAT each doped said second dopant type;
wherein said DBDL is within a fingertip drift region (FDR) associated with at least one of said drain fingertips (drain FDR) and said source fingertips (source FDR) between said first MOAT and said second MOAT, and
forming at least a first gate stack on said semiconductor surface between said source and said drain.

2. The method of claim 1 , wherein said respective stripe widths increase with an increasing angle θ relative to a boundary of said FDR with a linear drift region having a maximum width at 90 degrees.

3. The method of claim 1 , wherein said FDR includes said source FDR and said drain FDR.

4. The method of claim 1 , further comprising forming a top surface layer in said semiconductor surface doped said first dopant type.

5. The method of claim 1 , wherein said first gate stack comprises a split-gate including a first gate stack and a second gate stack lateral to said first gate stack.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Pendharkar Sameer P
• Balster Scott G

Classifications

• H10P30/22

  using masks · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L27/092

  Electricity · mapped topic

• H01L21/266

  Electricity · mapped topic