Semiconductor device
US-2015380400-A1 · Dec 31, 2015 · US
Insulated gate bipolar transistor structure having low substrate leakage
US8969913B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969913-B2 |
| Application number | US-201213673734-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 9, 2012 |
| Priority date | Dec 23, 2011 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.
First claim
Opening claim text (preview).
What is claimed is: 1. A high voltage semiconductor transistor, comprising: a lightly doped semiconductor substrate having a first type of conductivity; a buried layer in a first portion of the semiconductor substrate having a second type of conductivity; a first well region having the second type of conductivity and formed over the lightly doped semiconductor substrate, the first well region having a lower dopant concentration than the buried layer, the buried layer being par…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10D12/411Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969913B2 cover?
- A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source …
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg, Taiwan Semiconductor Maufacturing Company Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D12/411. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).