Method of making semiconductor device and system for performing the same

Patent metadata

Field	Value
Publication number	US-9639647-B2
Application number	US-201514625147-A
Country	US
Kind code	B2
Filing date	Feb 18, 2015
Priority date	Sep 27, 2013
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold.

First claim

What is claimed is:

1. A method of making a semiconductor device comprising:
determining, by a processor, a first pattern density of a first region;
determining, using the processor, a second pattern density of a second region;
determining, using the processor, a pattern density gradient from the first region to the second region;
determining, using the processor, whether the pattern density gradient exceeds a pattern density gradient threshold;
performing, using the processor, a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold; and
generating instructions, using the processor, for fabricating the semiconductor device based on the placement or the routing of the semiconductor device.

2. The method of claim 1 , wherein determining the first pattern density comprises determining the first pattern density of the first region having a first plurality of connected tiles, and determining the second pattern density comprises determining the second pattern density of the second region having a second plurality of connected tiles, wherein each tile of the first plurality of connected tiles and each tile of the second plurality of connected tiles has a pattern density.

3. The method of claim 1 , wherein determining the first pattern density comprises determining an average pattern density of the first region having a first plurality of connected tiles, and determining the second pattern density comprises determining an average pattern density of the second region having a second plurality of connected tiles, wherein each tile of the first plurality of connected tiles and each tile of the second plurality of connected tiles has a pattern density.

4. The method of claim 1 , wherein determining whether the pattern density gradient exceeds the pattern density gradient threshold comprises determining whether the pattern density gradient exceeds the pattern density gradient threshold that is 25% or greater.

5. The method of claim 1 , wherein determining the second pattern density comprises determining the second pattern density of the second region that is adjacent to the first region.

6. The method of claim 1 , wherein determining the first pattern density comprises determining the first pattern density of the first region having a first edge, and determining the second pattern density comprises determining the second pattern density of the second region having a second edge, wherein the first edge intersects the second edge.

7. The method of claim 1 , further comprising performing a design change if the pattern density gradient exceeds the pattern density gradient threshold, wherein the design change comprises one or more of:
moving a position of at least the first region or the second region of the semiconductor device;
filling a region of at least the first region or the second region of the semiconductor device;
adjusting a shape of at least the first region or the second region of the semiconductor device; or
adjusting a layout of at least the first region or the second region of the semiconductor device.

8. A method of making a semiconductor device comprising:
generating a floorplan comprising a plurality of connected tiles and a plurality of pattern densities, wherein each tile has a corresponding pattern density of the plurality of pattern densities;
determining, by a processor, a first pattern density of a first cell, the first cell comprising a first portion of the plurality of tiles;
determining a second pattern density of a second cell, the second cell comprising a second portion of the plurality of tiles;
determining a pattern density gradient from the first cell to the second cell based on the first pattern density and the second pattern density;
determining whether the pattern density gradient exceeds a pattern density gradient threshold;
performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold; and
fabricating the semiconductor device based on the placement or the routing of the semiconductor device.

9. The method of claim 8 , wherein generating the floorplan comprises generating the floorplan having the plurality of connected tiles, wherein at least one tile of the plurality of connected tiles has a shape chosen from rectangular, square or hexagonal.

10. The method of claim 8 , wherein determining the first pattern density of the first cell comprises determining an average of the pattern density of each tile contained in the first portion of the plurality of tiles, and determining the second pattern density of the second cell comprises determining an average of the pattern density of each tile contained in the second portion of the plurality of tiles.

11. The method of claim 8 , wherein determining the second pattern density comprises determining the second pattern density of the second cell that is adjacent to the first cell.

12. The method of claim 8 , wherein determining the first pattern density comprises determining the first pattern density of the first cell having a first edge, and determining the second pattern density comprises determining the second pattern density of the second cell having a second edge, wherein the first edge intersects the second edge.

13. The method of claim 8 , further comprising performing a design change if the pattern density gradient exceeds the pattern density gradient threshold, wherein the design change comprises one or more of:
moving a position of at least the first cell or the second cell of the semiconductor device;
filling a region of at least the first cell or the second cell of the semiconductor device;
adjusting a shape of at least the first cell or the second cell of the semiconductor device; or
adjusting a layout of at least the first cell or the second cell of the semiconductor device.

14. A system comprising:
a processor; and
a non-transitory computer readable medium connected to the processor, the non-transitory computer readable medium containing data representing an electronic design, the electronic design comprising a plurality of connected tiles and a plurality of pattern densities, wherein each tile has a corresponding pattern density of the plurality of pattern densities, and including instructions, which when executed by the processor, cause the processor to:
determine a first pattern density of a first cell, the first cell comprising a first portion of the plurality of tiles;
determine a second pattern density of a second cell, the second cell comprising a second portion of the plurality of tiles;
determine a pattern density gradient from the first cell to the second cell based on the first pattern density and the second pattern density;
determine whether the pattern density gradient exceeds a pattern density gradient threshold;
place or route the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold; and
generate instructions for fabricating the semiconductor device based on the placed or routed semiconductor device.

15. The system of claim 14 , wherein the instructions which, when executed by the processor, cause the processor to determine the first pattern density of the first cell comprises instructions which, when executed by the processor, to cause the processor to determine an average of the pattern density of each tile contained in the first portion of the plurality of tiles, and the instructions which, when executed by the processor, cause the processor to

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fu Chung-Min
• Lo Wan-Yu
• Liu Chin-Chou
• Tseng Huan Chi

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F17/5081

  Physics · mapped topic