System for designing a semiconductor device, device made, and method of using the system

Patent metadata

Field	Value
Publication number	US-9158883-B2
Application number	US-201213569717-A
Country	US
Kind code	B2
Filing date	Aug 8, 2012
Priority date	Aug 8, 2012
Publication date	Oct 13, 2015
Grant date	Oct 13, 2015

Abstract

This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.

First claim

What is claimed is:

1. A method of making a semiconductor device comprising:
generating layout style information based on a layout design of the semiconductor device, the layout style information comprising information regarding whether an active edge cell of the semiconductor device and a non-edge cell of the semiconductor device adjacent to the active edge cell have a distributed layout style that a plurality of electrically coupled gate electrode fingers is distributed in the active edge cell and the non-edge cell;
generating array edge information based on the layout design and a schematic design of the semiconductor device;
performing smart dummy insertion to selectively revise the layout design based on the layout style information and the array edge information;
performing a design rule check on the revised layout design based on the layout style information and the array edge information,
comprising determining whether a pattern density gradient at the active edge cell of the semiconductor device exceeds a threshold value; and
repeating the revising the layout design step if the pattern density gradient at the active edge cell exceeds the threshold value,
wherein at least one of the above operations is performed by a computer.

2. The method of claim 1 , wherein generating the array edge information comprises determining a location of the active edge cell and whether the layout design includes the one or more dummy cells.

3. The method of claim 1 , wherein determining whether a pattern density gradient exceeds a threshold value comprises determining whether the pattern density gradient at the active edge cell exceeds about 10% across an edge of the active edge cell.

4. The method of claim 1 , wherein performing a design rule check comprises examining a distance between the active edge cell located at an edge of the semiconductor device and an outside edge of the semiconductor device, wherein the distance is less than or equal to about 6 μm.

5. The method of claim 1 , further comprising performing a resistance-capacitance extraction of the schematic design.

6. The method of claim 1 , further comprising:
comparing the schematic design of the semiconductor device to the layout design of the semiconductor device to determine whether the layout design includes all features of the schematic design.

7. A system for manufacturing a semiconductor device comprising:
a layout style tool configured to generate layout style information based on a layout design of the semiconductor device, the layout style information comprising information regarding whether an active edge cell of the semiconductor device and a non-edge cell of the semiconductor device adjacent to the active edge cell have a distributed layout style that a plurality of electrically coupled gate electrode fingers is distributed in the active edge cell and the non-edge cell;
an array edge detection tool configured to generate array edge information based on the layout design and a schematic design of the semiconductor device;
a smart dummy cell insertion tool configured to selectively revise the layout design based on the layout style information received from the layout style tool and the array edge information received from the array edge detection tool in response to a condition that a pattern density gradient at the active edge cell of the semiconductor device exceeds a threshold value; and
a design rule checking (DRC) tool configured to perform a design rule check on the revised layout design based on the layout style information and the array edge information, comprising determining whether the pattern density gradient at the active edge cell of the semiconductor device exceeds the threshold value.

8. The system of claim 7 , wherein the array edge detection tool is configured to determine a location of the active edge cell and whether the layout design includes the one or more dummy cells.

9. The system of claim 7 , wherein the threshold value is about 10%.

10. The system of claim 7 , wherein the DRC tool is configured to examine a distance between the active edge cell and an outside edge of the semiconductor device.

11. The system of claim 10 , wherein the distance is less than or equal to about 6 μm.

12. The system of claim 7 , further comprising a resistance-capacitance (RC) extraction tool configured to perform an RC extraction simulation on the schematic design.

13. The system of claim 7 , further comprising:
a layout versus schematic (LVS) tool configured to compare the schematic design of the semiconductor device to the layout design of the semiconductor device.

14. A method of making a semiconductor device comprising:
generating layout style information based on a layout design of the semiconductor device, the layout style information comprising information regarding whether an edge cell of the semiconductor device and a non-edge cell of the semiconductor device adjacent to the edge cell have a distributed layout style that a plurality of electrically coupled gate electrode fingers is distributed in the edge cell and the non-edge cell;
generating array edge information based on the layout design and a schematic design of the semiconductor device, the generating the array edge information comprising:
determining if the layout design comprises a buffer zone outside and adjacent to a cell array, the buffer zone comprising one or more dummy cells;

performing smart dummy insertion to selectively revise the layout design based on the layout style information and the array edge information in response to a condition that a pattern density gradient at the edge cell of the semiconductor device exceeds a threshold value; and
performing a design rule check on the revised layout design based on the layout style information and the array edge information, comprising determining whether the pattern density gradient at the edge cell of the semiconductor device exceeds the threshold value,
wherein at least one of the above operations is performed by a computer.

15. The method of claim 14 , wherein the performing smart dummy insertion comprises:
modifying the layout design by inserting the buffer zone outside the cell array adjacent to the edge if it is determined that the layout design does not include the buffer zone.

16. The method of claim 14 , wherein the performing smart dummy insertion comprises:
modifying the layout design by reducing an area of the buffer zone if it is determined that the layout design includes the buffer zone and if it is determined that the edge cell and the non-edge cell have the distributed layout style.

Assignees

• Peng Yung-Chow
• Chou Wen-Shen
• Horng Jaw-Juinn
• Taiwan Semiconductor Mfg

Inventors

• Peng Yung-Chow
• Chou Wen-Shen
• Horng Jaw-Juinn

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5081 Primary

  Physics · mapped topic