Standard cell architecture for reduced leakage current and improved decoupling capacitance

Patent metadata

Field	Value
Publication number	US-9634026-B1
Application number	US-201615209650-A
Country	US
Kind code	B1
Filing date	Jul 13, 2016
Priority date	Jul 13, 2016
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

First claim

What is claimed is:

1. A standard cell integrated circuit (IC), comprising:
a plurality of p-type metal oxide semiconductor (MOS) (pMOS) transistors, each pMOS transistor of the plurality of pMOS transistors having a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate, each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors being coupled to a first voltage source, each pMOS transistor gate of the plurality of pMOS transistors being formed by a pMOS gate interconnect of a plurality of pMOS gate interconnects, each of the pMOS gate interconnects extending in a first direction and being coupled to the first voltage source; and
a plurality of n-type MOS (nMOS) transistors, each nMOS transistor of the plurality of nMOS transistors having an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate, each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors being coupled to a second voltage source lower than the first voltage source, each nMOS transistor gate of the plurality of nMOS transistors being formed by an nMOS gate interconnect of a plurality of nMOS gate interconnects, each of the nMOS gate interconnects extending in the first direction and being coupled to the second voltage source.

2. The standard cell IC of claim 1 , further comprising:
a first contact interconnect extending in a second direction orthogonal to the first direction and coupling the pMOS gate interconnects together, the first contact interconnect being coupled to the first voltage source; and
a second contact interconnect extending in the second direction and coupling the nMOS gate interconnects together, the second contact interconnect being coupled to the second voltage source.

3. The standard cell IC of claim 2 , wherein each pMOS gate interconnect of the plurality of pMOS gate interconnects is separated from and collinear with one nMOS gate interconnect of the plurality of nMOS gate interconnects in the first direction.

4. The standard cell IC of claim 2 , wherein the standard cell IC has n grids with pitch p between the grids, and a width of approximately n*p, the grids extending in the first direction, and wherein the plurality of pMOS transistors comprise n−3 transistors and the plurality of nMOS transistors comprise n−3 transistors, the standard cell IC further comprising:
a first dummy gate interconnect adjacent a first side of the standard cell IC and extending across the standard cell IC in the first direction, the first dummy gate floating; and
a second dummy gate interconnect adjacent a second side of the standard cell IC and extending across the standard cell IC in the first direction, the second dummy gate floating.

5. The standard cell IC of claim 4 , wherein the first contact interconnect and the second contact interconnect extend in the second direction between the first dummy gate interconnect and the second dummy gate interconnect.

6. The standard cell IC of claim 1 , wherein the standard cell IC has n grids with pitch p between the grids, and a width of approximately n*p, the grids extending in the first direction, and wherein the plurality of pMOS transistors comprise n−1 transistors and the plurality of nMOS transistors comprise n−1 transistors.

7. A method of operation of a standard cell integrated circuit (IC), comprising:
operating a plurality of p-type metal oxide semiconductor (MOS) (pMOS) transistors, each pMOS transistor of the plurality of pMOS transistors having a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate, each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors being coupled to a first voltage source, each pMOS transistor gate of the plurality of pMOS transistors being formed by a pMOS gate interconnect of a plurality of pMOS gate interconnects, each of the pMOS gate interconnects extending in a first direction and being coupled to the first voltage source; and
operating a plurality of n-type MOS (nMOS) transistors, each nMOS transistor of the plurality of nMOS transistors having an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate, each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors being coupled to a second voltage source lower than the first voltage source, each nMOS transistor gate of the plurality of nMOS transistors being formed by an nMOS gate interconnect of a plurality of nMOS gate interconnects, each of the nMOS gate interconnects extending in the first direction and being coupled to the second voltage source.

8. The method of claim 7 , wherein the standard cell IC further includes:
a first contact interconnect extending in a second direction orthogonal to the first direction and coupling the pMOS gate interconnects together, the first contact interconnect being coupled to the first voltage source; and
a second contact interconnect extending in the second direction and coupling the nMOS gate interconnects together, the second contact interconnect being coupled to the second voltage source.

9. The method of claim 8 , wherein each pMOS gate interconnect of the plurality of pMOS gate interconnects is separated from and collinear with one nMOS gate interconnect of the plurality of nMOS gate interconnects in the first direction.

10. The method of claim 8 , wherein the standard cell IC has n grids with pitch p between the grids, and a width of approximately n*p, the grids extending in the first direction, and wherein the plurality of pMOS transistors comprise n−3 transistors and the plurality of nMOS transistors comprise n−3 transistors, the standard cell IC further comprising:
a first dummy gate interconnect adjacent a first side of the standard cell IC and extending across the standard cell IC in the first direction, the first dummy gate floating; and
a second dummy gate interconnect adjacent a second side of the standard cell IC and extending across the standard cell IC in the first direction, the second dummy gate floating.

11. The method of claim 10 , wherein the first contact interconnect and the second contact interconnect extend in the second direction between the first dummy gate interconnect and the second dummy gate interconnect.

12. The method of claim 7 , wherein the standard cell IC has n grids with pitch p between the grids, and a width of approximately n*p, the grids extending in the first direction, and wherein the plurality of pMOS transistors comprise n−1 transistors and the plurality of nMOS transistors comprise n−1 transistors.

Assignees

• Qualcomm Inc

Inventors

• Sahu Satyanarayana
• Chen Xiangdong
• Vilangudipitchai Ramaprasath
• Kumar Dorav

Classifications

• H03K19/00361

  in field effect transistor circuits · CPC title

• H03K19/0008

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• H03K19/17736

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• H03K19/17728

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• H10D84/85

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