Continuous diffusion configurable standard cell architecture

Patent metadata

Field	Value
Publication number	US-9306570-B1
Application number	US-201514603262-A
Country	US
Kind code	B1
Filing date	Jan 22, 2015
Priority date	Jan 22, 2015
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain.

First claim

What is claimed is:

1. A semiconductor die comprising at least one configurable circuit cell comprising:
at least one center subcell, each of the at least one center subcell comprising:
a first p-type metal oxide semiconductor (pMOS) transistor having a first pMOS transistor gate, a first pMOS transistor source, and a first pMOS transistor drain, the first pMOS transistor source being coupled to a first voltage source;
a second pMOS transistor having a second pMOS transistor gate, a second pMOS transistor source, and a second pMOS transistor drain, the second pMOS transistor source being coupled to the first voltage source, the first pMOS transistor drain and the second pMOS transistor drain being a same drain;
a first n-type metal oxide semiconductor (nMOS) transistor having a first nMOS transistor gate, a first nMOS transistor source, and a first nMOS transistor drain, the first nMOS transistor source being coupled to a second voltage source; and
a second nMOS transistor having a second nMOS transistor gate, a second nMOS transistor source, and a second nMOS transistor drain, the second nMOS transistor source being coupled to the second voltage source, the first nMOS transistor drain and the second nMOS transistor drain being a same drain;

a first side subcell on a first side of the at least one center subcell; and
a second side subcell on a second side of the at least one center subcell, the at least one center subcell, the first side subcell, and the second side subcell having a continuous active region.

2. The semiconductor die of claim 1 , wherein the first pMOS transistor gate and the first nMOS transistor gate are separated and collinear, and the second pMOS transistor gate and the second nMOS transistor gate are separated and collinear.

3. The semiconductor die of claim 2 , wherein each center subcell further comprises:
a first interconnect coupling the first pMOS transistor gate to the second pMOS transistor gate; and
a second interconnect coupling the first nMOS transistor gate to the second nMOS transistor gate.

4. The semiconductor die of claim 3 , further comprising:
a third interconnect coupling the first interconnect to the first nMOS transistor drain and to the second nMOS transistor drain; and
a fourth interconnect coupling the second interconnect to the first pMOS transistor drain and to the second pMOS transistor drain.

5. The semiconductor die of claim 1 , wherein an edge of the continuous active region is within the first side subcell such that the first side subcell includes a break in the active region.

6. The semiconductor die of claim 1 , wherein an edge of the continuous active region is within the second side subcell such that the second side subcell includes a break in the active region.

7. The semiconductor die of claim 1 , wherein:
the first side subcell comprises a first-side-subcell pMOS transistor and a first-side-subcell nMOS transistor;
the first-side-subcell pMOS transistor has a first-side-subcell pMOS transistor gate, a first-side-subcell pMOS transistor source, and a first-side-subcell pMOS transistor drain;
the first-side-subcell nMOS transistor has a first-side-subcell nMOS transistor gate, a first-side-subcell nMOS transistor source, and a first-side-subcell nMOS transistor drain;
the first-side-subcell pMOS transistor gate and the first-side-subcell nMOS transistor gate are formed of one gate interconnect that extends across the configurable circuit cell;
the first-side-subcell pMOS transistor source is coupled to the first-side-subcell pMOS transistor drain and to the first voltage source;
the first-side-subcell nMOS transistor source is coupled to the first-side-subcell nMOS transistor drain and to the second voltage source; and
the first-side-subcell pMOS transistor gate and the first-side-subcell nMOS transistor gate are floating.

8. The semiconductor die of claim 7 , wherein:
the second side subcell comprises a first second-side-subcell pMOS transistor and a first second-side-subcell nMOS transistor;
the first second-side-subcell pMOS transistor has a first second-side-subcell pMOS transistor gate, a first second-side-subcell pMOS transistor source, and a first second-side-subcell pMOS transistor drain;
the first second-side-subcell nMOS transistor has a first second-side-subcell nMOS transistor gate, a first second-side-subcell nMOS transistor source, and a first second-side-subcell nMOS transistor drain;
the first second-side-subcell pMOS transistor gate and the first second-side-subcell nMOS transistor gate are formed of one gate interconnect that extends across the configurable circuit cell;
the first second-side-subcell pMOS transistor source is coupled to the first second-side-subcell pMOS transistor drain and to the first voltage source;
the first second-side-subcell nMOS transistor source is coupled to the first second-side-subcell nMOS transistor drain and to the second voltage source; and
the first second-side-subcell pMOS transistor gate and the first second-side-subcell nMOS transistor gate are floating.

9. The semiconductor die of claim 8 , wherein:
the second side subcell further comprises a second second-side-subcell pMOS transistor and a second second-side-subcell nMOS transistor;
the second second-side-subcell pMOS transistor has a second second-side-subcell pMOS transistor gate, a second second-side-subcell pMOS transistor source, and a second second-side-subcell pMOS transistor drain;
the second second-side-subcell nMOS transistor has a second second-side-subcell nMOS transistor gate, a second second-side-subcell nMOS transistor source, and a second second-side-subcell nMOS transistor drain;
the second second-side-subcell pMOS transistor gate and the second second-side-subcell nMOS transistor gate are formed of one gate interconnect that extends across the configurable circuit cell;
the second second-side-subcell pMOS transistor source, the second second-side-subcell pMOS transistor drain, the first second-side-subcell pMOS transistor source, and the first second-side-subcell pMOS transistor drain are all coupled together and to the first voltage source;
the second second-side-subcell nMOS transistor source, the second second-side-subcell nMOS transistor drain, the first second-side-subcell nMOS transistor source, and the first second-side-subcell nMOS transistor drain are all coupled together and to the second voltage source; and
the second second-side-subcell pMOS transistor gate and the second second-side-subcell nMOS transistor gate are floating.

10. The semiconductor die of claim 1 , wherein the configurable circuit cell has a configurable width w equal to w f +w s +n*w c , wherein w f is a width of the first side subcell, w s is a width of the second side subcell, and n*w c is a width of the at least one center subcell, where n is a number of center subcells of the at least one center subcell and w c is a width of each center subcell of the center subcells.

11. The semiconductor die of claim 10 , wherein the configurable circuit cell is configurable to be located within a region of an integrated circuit, the region having a width w r , wherein n is an integer such that w f +w s +n*w c ≦w r and w f +w s +(n+1)*w c >w r .

12. The semiconductor die of claim 1 , wherein the at least one center subcell comprises a plurality of center subcells that are each identical to each other.

13. The semiconductor die of claim 1 , further comprising additional configurable circuit cells, wherein the configurable circuit cells have various numbers of center subcells.

14. The semiconductor die of claim 13 , wherein said configurable circu

Assignees

• Qualcomm Inc

Inventors

• Sahu Satyanarayana
• Puckett Joshua Lance
• Kwon Ohsang
• Goodall Iii William James
• Bowers Benjamin John

Classifications

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• H03K19/17736

  Structural details of routing resources · CPC title

• H03K19/017581 Primary

  programmable · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H10D89/10

  Integrated device layouts · CPC title