Stacked common gate finFET devices for area optimization

Patent metadata

Field	Value
Publication number	US-9397101-B2
Application number	US-201414458228-A
Country	US
Kind code	B2
Filing date	Aug 12, 2014
Priority date	Mar 6, 2014
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.

First claim

What is claimed is:

1. A metal oxide semiconductor device, comprising:
a first fin field effect transistor (FinFET) having a first transistor source, a first transistor drain, a first transistor gate, and a set of first transistor fins, the set of first transistor fins extending from the first transistor gate and forming the first transistor source and the first transistor drain;
a second FinFET having a second transistor source, a second transistor drain, a second transistor gate, and a set of second transistor fins, the set of second transistor fins extending from the second transistor gate and forming the second transistor source and the second transistor drain;
a first gate interconnect extending linearly to form the first transistor gate and the second transistor gate and to connect together the first transistor gate and the second transistor gate, the first transistor drain and the second transistor source being on a first side of the first gate interconnect, the first transistor source and the second transistor drain being on a second side of the first gate interconnect;
a first interconnect on the first side of the first gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source;
a second interconnect on the second side of the first gate interconnect that connects together the set of first transistor fins at the first transistor source;
a third interconnect on the second side of the first gate interconnect that connects together the set of second transistor fins at the second transistor drain, the third interconnect being disconnected from the second interconnect;
a second gate interconnect extending adjacent one of the first transistor source and the second transistor drain or the first transistor drain and the second transistor source, the set of first transistor fins and the set of second transistor fins extending through the second gate interconnect.

2. The device of claim 1 , wherein the first FinFET and the second FinFET are p-type metal oxide semiconductor (pMOS) transistors.

3. The device of claim 1 , wherein the first FinFET and the second FinFET are n-type metal oxide semiconductor (nMOS) transistors.

4. The device of claim 1 , wherein the second gate interconnect extends adjacent the first transistor source and the second transistor drain, and the metal oxide semiconductor device further comprises a third gate interconnect extending adjacent the first transistor drain and the second transistor source.

5. The device of claim 4 , wherein the first transistor source is connected to a source voltage, and at least one of the second gate interconnect or the third gate interconnect is unconnected to a voltage such that the at least one of the second gate interconnect or the third gate interconnect is floating.

6. The device of claim 4 , wherein the first transistor source is connected to a source voltage, and the second and third gate interconnects are connected to the source voltage.

7. The device of claim 1 , further comprising:
a third FinFET having a third transistor source, a third transistor drain, a third transistor gate, and a set of third transistor fins, the set of third transistor fins extending from the third transistor gate and forming the third transistor source and the third transistor drain;
a fourth FinFET having a fourth transistor source, a fourth transistor drain, a fourth transistor gate, and a set of fourth transistor fins, the first gate interconnect extending linearly to form the third transistor gate and the fourth transistor gate and to connect together the first transistor gate, the second transistor gate, the third transistor gate, and the fourth transistor gate, the set of fourth transistor fins extending from the fourth transistor gate and forming the fourth transistor source and the fourth transistor drain, the third transistor drain and the fourth transistor source being on one of the first side or the second side of the first gate interconnect, the third transistor source and the fourth transistor drain being on an other one of the first side or the second side of the first gate interconnect;
a fourth interconnect on said one of the first side or the second side of the first gate interconnect that connects together the set of third transistor fins at the third transistor drain and the set of fourth transistor fins at the fourth transistor source;
a fifth interconnect on said other one of the first side or the second side of the first gate interconnect that connects together the set of third transistor fins at the third transistor source; and
a sixth interconnect on said other one of the first side or the second side of the first gate interconnect that connects together the set of fourth transistor fins at the fourth transistor drain, the fifth interconnect being disconnected from the sixth interconnect.

8. The device of claim 7 , first comprising:
a second gate interconnect extending adjacent the first transistor source and the second transistor drain;
a third gate interconnect extending adjacent the first transistor drain and the second transistor source;
a fourth gate interconnect extending adjacent the third transistor source and the fourth transistor drain; and
a fifth gate interconnect extending adjacent the third transistor drain and the fourth transistor source.

9. The device of claim 8 , wherein the first transistor source is connected to a first source voltage and the third transistor source is connected to a second source voltage, the second and third gate interconnects are unconnected to a voltage such that the second and third gate interconnects are floating, and the fourth and fifth gate interconnects are unconnected to a voltage such that the fourth and fifth gate interconnects are floating, wherein the second gate interconnect and the fourth gate interconnect are formed from one gate interconnect, and the third gate interconnect and the fifth gate interconnect are formed from one gate interconnect.

10. The device of claim 8 , wherein the first transistor source is connected to a first source voltage and the third transistor source is connected to a second source voltage, the second and third gate interconnects are connected to the first source voltage, and the fourth and fifth gate interconnects are connected to the second source voltage.

11. The device of claim 7 , further comprising a metal interconnect connecting the second transistor drain to the fourth transistor drain, wherein the first, second, third, and fourth FinFETs operate as an inverter with an input at the first gate interconnect and an output at the metal interconnect.

12. The device of claim 11 , further comprising:
a fifth FinFET having a fifth transistor source, a fifth transistor drain, a fifth transistor gate, and a set of fifth transistor fins, the set of fifth transistor fins extending from the fifth transistor gate and forming the fifth transistor source and the fifth transistor drain;
a sixth FinFET having a sixth transistor source, a sixth transistor drain, a sixth transistor gate, and a set of sixth transistor fins, the set of sixth transistor fins extending from the sixth transistor gate and forming the sixth transistor source and the sixth transistor drain;
a second gate interconnect extending linearly to form the fifth transistor gate and the sixth transistor gate and to connect together the fifth transistor gate and the sixth transistor gate, the fifth transistor drain and the sixth transistor source being on a first side of the second gate interconnect, the fifth transistor source and the sixth transistor drain being

Assignees

• Qualcomm Inc

Inventors

• Chintarlapalli Reddy Harikrishna
• Shah Jay Madhukar
• Gopalakrishna Ananth Haliyur

Classifications

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic