Metal nitride keyhole or spacer phase change memory cell structures

US9627612B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9627612-B2
Application numberUS-201514633264-A
CountryUS
Kind codeB2
Filing dateFeb 27, 2015
Priority dateFeb 27, 2014
Publication dateApr 18, 2017
Grant dateApr 18, 2017

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Abstract

Official abstract text for this publication.

Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure.

First claim

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What is claimed is: 1. A non-volatile memory device comprising: a bottom electrode embedded in an insulating substrate, said bottom electrode having a topmost surface that is coplanar with a topmost surface of said insulating substrate; a layer of dielectric material having a plurality of sidewall surfaces located within a via opening, said layer of dielectric material is located above said bottom electrode and said insulating substrate; a metal nitride spacer located along a bottom portion of each sidewall surface of said layer of dielectric material and in said via opening, said metal nitride spacer having a bottommost surface that present directly on a portion of said topmost surface of said bottom electrode, and a height that is less than a height of said dielectric layer; a phase change material structure present within said via opening and contacting at least a sidewall surface of said nitride spacer, said phase change material structure having a bottommost surface that is present directly on a remaining portion of said topmost surface of said bottom electrode; and a top electrode located on a topmost surface of said phase change material structure. 2. The non-volatile memory device of claim 1 , wherein said phase change material structure contacts a top portion of each sidewall surface of said layer of dielectric material and a topmost surface of of said metal nitride spacer. 3. The non-volatile memory device of claim 1 , wherein said phase change material is enclosed by said bottom electrode, said top electrode and said metal nitride spacer. 4. The non-volatile memory device of claim 1 , wherein said bottommost surface of said phase change material structure is coplanar with said bottommost surface of said metal nitride spacer. 5. The non-volatile memory device of claim 1 , wherein said metal nitride spacer comprises a compound M-X—N wherein M is Ti or Ta, and X is Al or Si. 6. The non-volatile memory device of claim 1 , wherein said phase change memory material structure comprises a chalcogenide. 7. The non-volatile memory device of claim 1 , wherein one sidewall surface of said metal nitride layer extends beyond a vertical edge of said bottom electrode and a portion of said bottommost surface of said metal nitride spacer directly contacts said topmost surface of said insulating substrate. 8. The non-volatile memory device of claim 1 , wherein one sidewall surface of said metal nitride spacer is vertically coincident to a vertical edge of said bottom electrode and an entirety of said bottommost surface of said metal nitride spacer directly contacts an exposed portion of said topmost surface of said bottom electrode. 9. The non-volatile memory device of claim 1 , wherein a topmost surface of said metal nitride spacer is coplanar with said topmost surface of said phase change material structure. 10. The non-volatile memory device of claim 9 , wherein a topmost surface of said top electrode is coplanar with a topmost surface of said layer of dielectric material.

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What does patent US9627612B2 cover?
Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L45/06. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).