Resistance memory device

Patent metadata

Field	Value
Publication number	US-9012880-B2
Application number	US-201313773612-A
Country	US
Kind code	B2
Filing date	Feb 21, 2013
Priority date	Feb 21, 2013
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.

First claim

What is claimed is:

1. A resistance memory device, comprising:
a dielectric layer, disposed on a substrate and has a first opening constituted by a lower opening and an upper opening;
a conductive layer, filling up the lower opening;
a bottom electrode, disposed on a bottom and on at least a portion of a sidewall of the upper opening;
a top electrode, disposed in the upper opening without contacting the sidewall of the upper opening; and
a variable resistance layer, disposed between the bottom electrode and the top electrode,
wherein the bottom electrode exposes a top portion of the sidewall of the upper opening, and the variable resistance layer covers the exposed top portion of the sidewall of the upper opening.

2. The resistance memory device of claim 1 , wherein a sidewall of the lower opening is aligned with a sidewall of the upper opening.

3. The resistance memory device of claim 1 , wherein a thickness of the bottom electrode on the sidewall of the upper opening is less than a thickness of the bottom electrode on the bottom of the upper opening.

4. The resistance memory device of claim 1 , wherein the dielectric layer further has a second opening, and the conductive layer further fills up the second opening.

5. The resistance memory device of claim 4 , wherein the first opening and the second opening penetrate through the dielectric layer.

6. The resistance memory device of claim 5 , further comprising a metal layer disposed on the dielectric layer and electrically connected to the top electrode and the conductive layer within the second opening.

7. The resistance memory device of claim 1 , wherein the conductive layer is electrically connected to another conductive layer disposed below the dielectric layer.

8. The resistance memory device of claim 7 , wherein the another conductive layer comprises a doped region, a polysilicon layer or a metal layer.

Assignees

• Winbond Electronics Corp

Inventors

• Jang Wen-Yueh
• Chiang Ming-Chung

Classifications

• H01L45/1273

  Electricity · mapped topic

• H01L45/1233 Primary

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic

• H01L45/1666

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic