Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9373785-B2
Application number	US-201113048500-A
Country	US
Kind code	B2
Filing date	Mar 15, 2011
Priority date	Mar 30, 2010
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.

First claim

What is claimed is:

1. A memory device comprising: a first electrode; a second electrode;
an ion source layer between the first and second electrodes and containing at least one element selected from the group consisting of Cu, Ag, Zn, Al, and Zr and at least one element selected from the group consisting of Te, S, and Se;
a memory layer between the first electrode and the ion source layer and storing information by a variation of a resistance value, the memory layer made of a material selected from the group consisting of oxides of Ta, Nb, Al, Hf, Zr, Ni, Co, and Ce;
an insulation layer that isolates the memory layer and the ion source layer; and
a diffusion preventing barrier at a periphery of the memory layer and the ion source layer, wherein,
the diffusion preventing barrier (a) having a bottom surface on a top surface of the first electrode, the bottom surface of the diffusion preventing barrier coinciding with a bottom surface of the memory layer, (b) having a top surface coinciding with a top surface of the ion source layer, (c) extending continuously along the periphery of the memory layer and the ion source layer and abutting the bottom surface of the second electrode,
wherein, the diffusion preventing barrier comprises (i) an oxide of a metal element selected from the group consisting of Ti, Ru, Mn, Al, Co, and W, (ii) a nitride of a metal element selected from the group consisting of Ti, Ru, Mn, Al, Co, and W, or (iii) an alloy of any of a metal element selected from the group consisting of Ti, Ru, Mn, Al, Co, and W.

2. The memory device according to claim 1 , wherein the diffusion preventing barrier is formed between (a) the insulation layer, and (b) the memory layer and the ion source layer.

3. The memory device according to claim 2 , wherein the diffusion preventing barrier is made from amorphous SiN or amorphous SiCN.

4. The memory device according to claim 1 , wherein the insulation layer also serves as a diffusion preventing barrier.

5. The memory device according to claim 4 , wherein the diffusion preventing barrier is made from a nitrogen-containing resin material.

6. The memory device according to claim 1 , wherein, when a voltage is applied to the memory layer and the ion source layer, an element that is contained in the ion source layer diffuses into the inside of the memory layer as an ion, and a conduction path is formed in the memory layer, such that a resistance value of the memory layer becomes lowered.

7. A memory device comprising: a first electrode; a second electrode;
an ion source layer between the first and second electrodes and containing at least one element selected from the group consisting of Cu, Ag, Zn, Al, and Zr and at least one element selected from the group consisting of Te, S, and Se;
a memory layer between the ion source layer and the first electrode and that stores information by a variation of a resistance value, the memory layer made of a material selected from the group consisting of oxides of Ta, Nb, Al, Hf, Zr, Ni, Co, and Ce;
an insulation layer that isolates the memory layer and the ion source layer; and
a diffusion preventing barrier at a periphery of the second electrode layer, the memory layer and the ion source layer, wherein,
the diffusion preventing barrier (a) having a bottom surface on a top surface of the first electrode, the bottom surface of the diffusion preventing barrier coinciding with a bottom surface of the memory layer, (b) having a top surface coinciding with a top surface of the ion source layer, and (c) extending continuously along the periphery of the memory layer and the ion source layer, and abutting a bottom surface of the second electrode;
the diffusion preventing barrier comprises (i) an oxide of a metal element selected from the group consisting of Ti, Ru, Mn, Al, Co, and W, (ii) a nitride of a metal element selected from the group consisting of Ti, Ru, Mn, Al, Co, and W, or (iii) an alloy of any of a metal element selected from the group consisting of Ti, Ru, Mn, Al, Co, and W, and the memory layer has a lower surface facing an upper surface of the first electrode the upper surface of the first electrode having a surface area greater than the lower surface of the memory layer.

8. The memory device according to claim 7 , wherein the diffusion preventing barrier is formed between (a) the insulation layer, and (b) the memory layer and the ion source layer.

9. The memory device according to claim 8 , wherein the diffusion preventing barrier is made from amorphous SiN or amorphous SiCN.

10. The memory device according to claim 7 , wherein the insulation layer also serves as a diffusion preventing barrier.

11. The memory device according to claim 10 , wherein the diffusion preventing barrier is made from a nitrogen-containing resin material.

12. The memory device according to claim 7 , wherein, when a voltage is applied to the memory layer and the ion source layer, an element that is contained in the ion source layer diffuses into the inside of the memory layer as an ion, and a conduction path is formed in the memory layer, such that a resistance value of the memory layer becomes lowered.

Assignees

• Kagawa Yoshihisa
• Sony Corp

Inventors

• Kagawa Yoshihisa

Classifications

• H01L27/112

  Electricity · mapped topic

• H01L45/12

  Electricity · mapped topic

• H01L45/124

  Electricity · mapped topic

• H01L45/1625

  Electricity · mapped topic

• H01L45/1266

  Electricity · mapped topic