Interleaved Δ-Σ modulator

Patent metadata

Field	Value
Publication number	US-9621183-B2
Application number	US-201514745354-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Jun 20, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.

First claim

What is claimed is:

1. A modulator comprising:
a. a forward path coupling a input summing block with an data out block, the forward path including at least a Nth order filter coupled to said input summing block and a plurality of interleaved multi-bit Analog to Digital Converters (ADCs), the interleaved multi-bit ADCs the having inputs which are coupled to said Nth order filter and outputs which are coupled to said data out block; and
b. a feedback path including a plurality of interleaved multi-bit Digital to Analog Converters (DACs), the interleaved multi-bit DACs having inputs which are coupled to respective outputs of the interleaved multi-bit ADCs, the interleaved multi-bit DACs having outputs which are summed together and applied to said input summing block, with connections between the interleaved multi-bit DACs and the Nth order filter.

2. The modulator of claim 1 wherein the data out block includes at least a decoder and a demultiplexer coupled in series between the outputs of the interleaved multi-bit ADCs and an output of the modulator, the decoder having a plurality of inputs coupled directly to the outputs of the interleaved multi-bit ADCs.

3. The modulator of claim 2 wherein the interleaved multi-bit ADCs output digital data in a thermometer code and the decoder translates thermometer coded data from the interleaved multi-bit ADCs into a gray or binary code.

4. The modulator of claim 1 wherein the input summing block combines an input RF stream of analog data to the modulator with the outputs of the interleaved multi-bit DACs, so that, in use, analog data at the outputs of the interleaved multi-bit DACs is subtracted from the input RF stream of analog data.

5. The modulator of claim 4 wherein the input summing block includes a Low Noise Transconductance Amplifier (LNTA) which has an input thereof coupled to the input RF stream of analog data and an output connected to the outputs of the interleaved multi-bit DACs and to an input of the Nth order filter.

6. The modulator of claim 4 wherein the input summing block includes a coupler having inputs coupled to the input RF stream of analog data and to the outputs of the interleaved multi-bit DACs and at least one output, the input summing block further including a Low Noise Transconductance Amplifier (LNTA) which has an input thereof coupled the at least one output of said coupler and having an output coupled to an input of the Nth order filter.

7. The modulator of claim 1 wherein the connections from the interleaved multi-bit DACs to the Nth order filter include at least one stability compensation circuit coupled to a plurality of summing nodes within said Nth order filter.

8. The modulator of claim 7 wherein the stability compensation circuit has inputs coupled at the inputs of the interleaved multi-bit DACs and a plurality of outputs individually coupled to said plurality of summing nodes in said Nth order filter.

9. The modulator of claim 8 wherein a final summing node in said Nth order filter receives the most significant bits available at the inputs of the interleaved multi-bit DACs via a plurality of one-bit DACs.

10. The modulator of claim 7 wherein the stability compensation circuit has a plurality one-bit DACs coupling data available at the inputs of the interleaved multi-bit DACs to said plurality of summing nodes within said Nth order filter.

11. The modulator of claim 7 wherein the stability compensation circuit has a plurality one-bit DACs coupling data available at the outputs of the interleaved multi-bit DACs to said separate summing nodes within said Nth order filter.

12. The modulator of claim 1 wherein the Nth order filter is a bandpass filter.

13. The modulator of claim 1 wherein the Nth order filter is a lowpass filter.

14. The modulator of claim 12 wherein the Nth order filter is a 6th order filter having three resonant circuits therein.

15. The modulator of claim 12 wherein the plurality of interleaved multi-bit ADCs comprise a pair of interleaved three-bit ADCs, wherein the plurality of interleaved multi-bit DACs comprise a pair of interleaved three-bit DACs.

16. The modulator of claim 1 wherein the plurality of interleaved multi-bit ADCs comprise a plurality of ladder circuits each coupled in series with a comparator circuit for generating a digital thermometer code corresponding to analog data provided to said ladder circuits.

17. The modulator of claim 1 wherein the Nth order filter has a plurality, and preferably N/2, resonators coupled in series between a filter input and a filter output t.

18. The modulator of claim 17 wherein the resonators have fixed resonate frequencies.

19. The modulator of claim 17 wherein the resonators have variable resonate frequencies set by digitally controlled filter values.

20. The modulator of claim 19 wherein the digitally controlled filter values are derived from a digital signal processor coupled to said data out block.

21. The modulator of claim 18 further including a plurality of multi-bit DACs having inputs controlled by said digital signal processor and having outputs coupled to the plurality of transconductance amplifiers in said Nth for filter for controlling the gains thereof.

22. A analog to digital converter comprising the modulator of claim 2 and a decimator coupled to the output of the modulator of claim 2 .

23. A method increasing the dynamic range of a ΔΣ modulator comprising:
providing a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs being connected in a loop, wherein the number of ADCs in said plurality of ADCs is equal to M;
coupling the plurality of ADCs with an incoming analog signal having a maximum frequency f;
controlling said plurality of ADCs and plurality of DACs with a plurality of clock signals each having a frequency equal to a multiple of f, the clock signals in said plurality of clock signals being offset relative to each other in the time domain thereby enabling each ADC in said plurality of ADCs one at a time and enabling each DAC in said plurality of DACs one at a time such that the ΔΣ modulator processes data in said incoming analog signal in an interleaved fashion;
increasing a number of bits processed in parallel by each ADC in said plurality of ADCs and each DAC in said plurality of DACs such that each each ADC in said plurality of ADCs is a multibit ADC and each DAC in said plurality of DACs is a multibit DAC; and
applying the incoming analog signal to a summing junction along with outputs from the plurality of DACs and filtering data output from the summing junction by an Nth order filter having a plurality of internal summing junctions, the internal summing junctions also being connected with said plurality of DACs, and applying an output of the Nth order filter to the plurality of ADCs in said interleaved fashion.

24. The method of claim 23 wherein the number of bits processed a one time by each of said ADCs is equal to K, with M preferably being equal to 2 and K preferably being equal to 3.

25. The modulator of claim 1 wherein said connections occur externally of said summing block between the interleaved multi-bit DACs and the Nth order filter.

26. The modulator of claim 25 wherein the connections include a plurality one-bit DACs coupling data available at the inputs of the interleaved multi-bit DACs to summing nodes within said Nth order filter.

27. The modulator of clai

Assignees

• Hrl Lab Llc
• Hrl Lab Llc

Inventors

• Baringer Cynthia D
• Xu Zhiwei A
• Petre Peter
• Hitko Donald A
• Cosand Albert

Classifications

• H03M3/46

  using a combination of at least one delta-sigma modulator in series with at least one analogue/digital converter of a different type · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/37

  Compensation or reduction of delay or phase error · CPC title

• H03M3/47 Primary

  using time-division multiplexing · CPC title

• H03M1/066

  by continuously permuting the elements used, i.e. dynamic element matching · CPC title