Delay-free poly-phase quantizer and quantization method for PWM mismatch shaping

Patent metadata

Field	Value
Publication number	US-10164650-B2
Application number	US-201715435155-A
Country	US
Kind code	B2
Filing date	Feb 16, 2017
Priority date	Feb 16, 2017
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

First claim

What is claimed is:

1. A delta-sigma modulator for pulse-width modulation (PWM) mismatch shaping, the delta-sigma modulator comprising:
a first PWM modulator having a first input terminal, a second input terminal, and an output terminal;
a voltage ramp generator having an output terminal coupled to the second input terminal of the first PWM modulator;
a first delay element having an input terminal and an output terminal, the input terminal of the first delay element being coupled to the output terminal of the voltage ramp generator;
a second PWM modulator having a first input terminal coupled to the first input terminal of the first PWM modulator, a second input terminal, and an output terminal, the second input terminal of the second PWM modulator being coupled to the output terminal of the first delay element;
a second delay element having an input terminal coupled to the output terminal of the first delay element;
a third PWM modulator having a first input terminal coupled to the first input terminal of the first PWM modulator and a second input terminal coupled to the output terminal of the second delay element; and
a loop filter having a first input terminal, a second input terminal, and an output terminal, the output terminal of the loop filter coupled to the first input terminal of the first PWM modulator and to the first input terminal of the second PWM modulator.

2. The delta-sigma modulator of claim 1 , wherein the voltage ramp generator generates a sequence of reference voltages based on a transfer function of a digital word stored in a counter circuit.

3. The delta-sigma modulator of claim 1 , further comprising a combiner having a first input terminal coupled to the output terminal of the first PWM modulator, a second input terminal coupled to the output terminal of the second PWM modulator, and an output terminal coupled to the second input terminal of the loop filter.

4. The delta-sigma modulator of claim 3 , wherein the loop filter being adapted to receive a multi-bit pulse code modulated (PCM) signal and the combiner being adapted to generate a multi-bit pulse density modulated (PDM) signal.

5. The delta-sigma modulator of claim 4 , wherein the first PWM modulator generates a first single-bit PWM signal and the second PWM modulator generates a second single-bit PWM signal.

6. The delta-sigma modulator of claim 5 , wherein the first PWM modulator generates a first single-bit PWM signal by comparing a first voltage on the first terminal of the first PWM modulator to a second voltage on the second input terminal of the first PWM modulator.

7. The delta-sigma modulator of claim 1 , wherein the first delay element delays a signal by a first delay amount, wherein the second delay element delays a signal by a second delay amount, and wherein the first delay amount and the second delay amount being equal to one period of a sampling clock signal.

8. A delta-sigma modulator for pulse-width modulation (PWM) mismatch shaping, the delta-sigma modulator comprising:
a first PWM modulator having a first input terminal, a second input terminal, and an output terminal;
a voltage ramp generator having an output terminal coupled to the second input terminal of the first PWM modulator;
a second PWM modulator having a first input terminal, a second input terminal, and an output terminal;
a local filter having an input terminal and an output terminal, the output terminal of the local filter being coupled to the first input terminal of the first PWM modulator;
a subtractor having a first and second input terminal and an output terminal, the output terminal being coupled to the input terminal of the local filter; and
a loop filter having a first input terminal, a second input terminal, and an output terminal, the output terminal of the loop filter being coupled to the first input terminal of the subtractor.

9. The delta-sigma modulator of claim 8 , further comprising:
another local filter having an input terminal and an output terminal, the output terminal of the other local filter being coupled to the first input terminal of the second PWM modulator; and
another subtractor having first and second input terminals and an output terminal, the output terminal being coupled to the input terminal of the other local filter.

10. The delta-sigma modulator of claim 8 , wherein the voltage ramp generator generates a sequence of reference voltages based on a transfer function of a digital word stored in a counter circuit.

11. The delta-sigma modulator of claim 8 , the second input terminal of the subtractor being coupled to the output terminal of the first PWM modulator.

12. The delta-sigma modulator of claim 11 , further comprising a first delay element having an input terminal coupled to the output terminal of the voltage ramp generator and an output terminal coupled to the second input terminal of the second PWM modulator.

13. The delta-sigma modulator of claim 12 , the delta-sigma modulator further comprising:
a second delay element having an input terminal coupled to the output terminal of the first delay element; and
a third PWM modulator having a first input terminal coupled to the output terminal of a second local filter and a second input terminal coupled to the output terminal of the second delay element.

14. The delta-sigma modulator of claim 13 , wherein the first delay element delays a signal by a first delay amount, the second delay element delays a signal by a second delay amount, and the first delay amount and the second delay amount being equal to one period of a sampling clock.

15. The delta-sigma modulator of claim 12 , further comprising a combiner having a first input terminal coupled to the output terminal of the first PWM modulator, a second input terminal coupled to the output terminal of the second PWM modulator, and an output terminal coupled to the second input terminal of the loop filter.

16. The delta-sigma modulator of claim 15 , wherein the loop filter is adapted to receive a multi-bit pulse code modulated (PCM) signal and the combiner is adapted to generate a multi-bit pulse density modulated (PDM) signal.

17. The delta-sigma modulator of claim 12 , wherein the first PWM modulator generates a first single-bit PWM signal and the second PWM modulator generates a second single-bit PWM signal.

18. The delta-sigma modulator of claim 17 , wherein the first PWM modulator generates a first single-bit PWM signal by comparing a first voltage on the first terminal of the first PWM modulator to a second voltage on the second input terminal of the first PWM modulator.

19. A method for pulse-width modulation (PWM) mismatch shaping, the method comprising:
receiving a multi-bit pulse-code modulated (PCM) signal;
generating a voltage ramp signal;
generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal;
generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal;
delaying the voltage-ramp signal;
generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal;
generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal; and
generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

20. The method of claim 19 , wherein generating the first corrected signal comprises subtracting the first feedback signal from the multi-bit PCM signal, and where

Assignees

• Qualcomm Inc

Inventors

• Lu Jingxue
• Sienko Matthew

Classifications

• H03M1/0617 Primary

  characterised by the use of methods or means not specific to a particular type of detrimental influence · CPC title

• H03M3/50

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03M3/42 Primary

  having multiple quantisers arranged in parallel loops · CPC title

• H03M3/432

  the quantiser being a pulse width modulation type analogue/digital converter, i.e. differential pulse width modulation · CPC title

• H03M3/47

  using time-division multiplexing · CPC title