Nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9165643-B2
Application number	US-201414562904-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Aug 24, 2012
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

This nonvolatile semiconductor memory device comprises a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element. A third line extends through a plurality of the memory mats. A second variable resistance element is connected between the third line and the second line of each of the plurality of memory mats.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a memory cell array configured having a plurality of memory mats arranged therein, each of the memory mats having a memory cell disposed therein at an intersection of a first line and a second line, the memory cell including a first variable resistance element;
a third line extending through a plurality of the memory mats; and
a second variable resistance element connected between the third line and…

Assignees

• Toshiba Kk

Inventors

• Ichige Masayuki

Classifications

• G11C5/025 Primary

  Physics · mapped topic

• G11C8/12

  Physics · mapped topic

• G11C7/18

  Physics · mapped topic

• G11C13/0002 Primary

  Physics · mapped topic