Integrated circuits including magnetic core inductors and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9613897-B2
Application number	US-201414537942-A
Country	US
Kind code	B2
Filing date	Nov 11, 2014
Priority date	Nov 11, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.

First claim

What is claimed is:

1. An integrated circuit comprising a magnetic core inductor, the magnetic core inductor comprising:
a bottom magnetic plate comprising a center portion and first, second, third, and fourth extension portions extending from the center portion;
an interlayer dielectric layer disposed over the bottom magnetic plate;
within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion, each of the first through fifth via trenches comprising a magnetic material along sidewalls thereof and being filled with a high dielectric breakdown material;
a stacked-ring inductor coil comprising a plurality of inductor rings surrounding the fifth via trench; and
a top magnetic plate comprising a center portion and first, second, third, and fourth extension portions extending from the center portion that lie over respective ones of the center, first, second, third, and fourth extension portions of the bottom magnetic plate.

2. The integrated circuit of claim 1 , wherein the magnetic core inductor lies over a back-end-of-line stack that comprises one or more metallization layers and one or more dielectric layers.

3. The integrated circuit of claim 2 , wherein the back-end-of-line stack lies over a semiconductor substrate that comprises one or more of transistors, resistors, diodes, capacitors, inductors, and fuses.

4. The integrated circuit of claim 1 , wherein the bottom magnetic plate, the magnetic material along the sidewalls of the via trenches, and the top magnetic plate each independently comprise a material that is selected from the group consisting of: Co, Fe, Ni, Mo, NiFe, NiFeMo, CoNbZr, CoMoNiFe, FeAlO, FeSi, and combinations thereof.

5. The integrated circuit of claim 1 , wherein adjacent extension portions of the bottom and top magnetic plate are separated from one another by an angle of from about 45 degrees to about 135 degrees.

6. The integrated circuit of claim 5 , wherein adjacent extension portions of the bottom and top magnetic plate are separated from one another by an angle of about 90 degrees, and wherein the bottom and top magnetic plates are substantially plus-shaped.

7. The integrated circuit of claim 1 , wherein the via trenches are substantially cylindrically shaped.

8. The integrated circuit of claim 1 , wherein the stacked-ring inductor coil is substantially circularly shaped, or is shaped in the form of a rectangle having rounded edges or a square having rounded edges.

9. The integrated circuit of claim 1 , wherein the stacked-ring inductor coil is separated from the fifth via trench by portions of the interlayer dielectric layer.

10. The integrated circuit of claim 1 , wherein each of the first, second, third, and fourth via trenches are not surrounded by any inductor rings.

11. The integrated circuit of claim 1 , wherein the inductor stacked-ring inductor coil comprises at least three inductor rings.

12. The integrated circuit of claim 1 , wherein the inductor rings comprise a copper material or a copper alloy.

13. The integrated circuit of claim 1 , wherein the high dielectric breakdown material comprises a polyimide material.

14. The integrated circuit of claim 1 , further comprising contact terminal pads that are electrically coupled with the stacked-ring inductor coil disposed over the high dielectric breakdown material.

15. A method for fabricating an integrated circuit that comprises a magnetic core inductor, the method comprising:
forming a bottom magnetic plate layer over a back-end-of-line stack layer;
patterning the bottom magnetic plate layer into a shape that comprises a center portion and first, second, third, and fourth extension portions extending from the center portion;
forming an interlayer dielectric layer with a stacked-ring inductor coil therein over the patterned bottom magnetic plate layer, wherein the stacked-ring inductor coil is formed over the center portion of the bottom magnetic plate layer and comprises a plurality of inductor rings;
etching first, second, third, fourth, and fifth via trenches into the interlayer dielectric layer, wherein the first through fourth via trenches are formed over respective ones of the first through fourth extension portions of the patterned bottom magnetic plate layer, and wherein the fifth via trench is formed over the center portion of the patterned bottom magnetic layer and within the inductor rings of the stacked-ring inductor coil;
forming magnetic material sidewall liners along sidewalls of each of the first through fifth via trenches;
forming a top magnetic plate layer over the interlayer dielectric layer;
patterning the top magnetic plate layer into a shape that comprises a center portion and first, second, third, and fourth extension portions extending from the center portion that align with respective ones of the first, second, third, fourth, and center portions of the patterned bottom magnetic plate layer; and
filling the first through fifth trenches with a high dielectric breakdown material.

16. The method of claim 15 , further comprising forming the back-end-of- line stack layer over a semiconductor substrate layer.

17. The method of claim 15 , further comprising forming conductive terminal pads over the high dielectric breakdown material.

18. The method of claim 15 , wherein forming the interlayer dielectric layer with the stacked-ring inductor coil therein comprises forming an interlayer dielectric layer comprising at least three inductor rings.

19. The method of claim 15 , wherein forming bottom magnetic plate layer, the magnetic material sidewall liners, and the top magnetic plate layer each comprise, independently, forming layers of a material that is selected from the group consisting of: Co, Fe, Ni, Mo, NiFe, NiFeMo, CoNbZr, CoMoNiFe, FeAlO, FeSi, and combinations thereof.

20. An integrated circuit comprising a magnetic core inductor, the magnetic core inductor comprising:
first, second, and third via trenches formed within an interlayer dielectric layer and formed in a substantially co-linear configuration with respect to one another, wherein the second via trench is disposed linearly between the first and second via trenches, wherein a first portion of the interlayer dielectric layer separates the first via trench from the second via trench, and wherein a second portion of the interlayer dielectric layer separates the second via trench from the third via trench;
a magnetic material layer disposed at a bottom portion of each of the via trenches, along sidewalls of each of the via trenches, underneath the first and second portions of interlayer dielectric layer, and above the first and second portions of the interlayer dielectric layer; and
a stacked-ring inductor coil comprising a plurality of inductor rings formed within the first and second portions of the interlayer dielectric layer and surrounding the second via trench.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Bhatkar Mahesh
• Peng Lulu
• Yi Wanbing
• Tan Juan Boon
• England Luke

Classifications

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H01L28/10

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L23/5227 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic