Donor cores to improve integrated circuit yield

Patent metadata

Field	Value
Publication number	US-9612988-B2
Application number	US-201313948805-A
Country	US
Kind code	B2
Filing date	Jul 23, 2013
Priority date	Jul 23, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A device uses donor circuit blocks in a donor integrated circuit to replace defective circuit blocks in a recipient integrated circuit and create a functional integrated circuit. The recipient integrated circuit has a first number of cores, the first number including a recipient core, and the recipient core having a recipient circuit block, a switching element, and a recipient communication point, the first number of cores connected by a data bus. The recipient core has an intended function. The donor integrated circuit has a second number of cores, the second number smaller than the first number. The second number includes a donor core having a donor communication point electrically connected to a donor circuit block, the donor circuit block having the intended function. The recipient connection point is electrically connected to the donor connection point and the switching element switched to disable the recipient circuit block in the recipient core.

First claim

What is claimed is:

1. A device comprising:
a recipient integrated circuit having a data bus and a first number of cores, the first number of cores including a recipient core, the recipient core having a switching element, a recipient communication point, and a recipient circuit block, the recipient circuit block having an intended function, the switching element connected to the data bus, the recipient circuit block, and the recipient communication point; and
a donor integrated circuit having a second number of cores, the second number less than the first number, the second number of cores including a donor core, the donor core having a donor circuit block connected to a donor communication point, the donor circuit block having the intended function, the donor communication point being electrically connected to the recipient communication point;
wherein the first number of cores includes a second recipient core, the second recipient core having a second switching element, a second recipient communication point, and a second recipient circuit block, the second recipient circuit block having a second intended function, the second switching element connected to the data bus, the second recipient circuit block, and the second recipient communication point,
the device further comprising: a second donor integrated circuit having a third number of cores, the third number less than the first number, the third number of cores including a second donor core, the second donor core having a second donor circuit block connected to a second donor communication point, the second donor circuit block having the second intended function, the second donor communication point being electrically connected to the second recipient communication point.

2. The device of claim 1 , wherein the recipient core is selected from the group consisting of a logic circuit element, a graphical processing circuit element, an input/output circuit element, and a memory circuit element.

3. The device of claim 1 , wherein the second number is equal to one.

4. The device of claim 1 , wherein the second number is equal to one, and wherein the third number is equal to one.

5. The device of claim 1 , wherein a recipient communication element connects the switching element and the recipient communication point, the recipient communication element including at least one through-silicon via.

6. The device of claim 1 , wherein a donor communication element connects the donor circuit block and the donor communication point, the donor communication element including at least one through-silicon via.

7. The device of claim 1 , wherein a chip connection element connects the recipient communication point and the donor communication point, the chip connection element created by at least one of wirebonding and soldering.

8. A method of appending a donor integrated circuit to a recipient integrated circuit, the method comprising:
providing the recipient integrated circuit having a data bus and a first number of cores, the first number of cores including a recipient core, the recipient core having a switching element, a recipient communication point, and a recipient circuit block, the recipient circuit block having an intended function, the switching element connected to the data bus, the recipient circuit block, and the recipient communication point;
providing the donor integrated circuit having a second number of cores, the second number less than the first number, the second number of cores including a donor core, the donor core having a donor circuit block electrically connected to a donor communication point, the donor circuit block having the intended function;
providing a second recipient core, the second recipient core having a second switching element, a second recipient communication point, and a second recipient circuit block, the second recipient circuit block having a second intended function, the second switching element connected to the data bus, the second recipient circuit block, and the second recipient communication point;
providing a second donor integrated circuit having a third number of cores, the third number less than the first number, the third number of cores including a second donor core, the second donor core having a second donor circuit block connected to a second donor communication point, the second donor circuit block having the second intended function;
electrically connecting the recipient communication point to the donor communication point;
electrically connecting the second recipient communication point to the second donor communication point;
switching the switching element to disable the recipient circuit block and enable the donor circuit block; and
switching the second switching element to disable the second recipient circuit block and enable the second donor circuit block.

9. The method of claim 8 , wherein the recipient communication point is electrically connected to the donor communication point by at least one of soldering and wirebonding.

10. The method of claim 8 , wherein the recipient core is selected from the group consisting of a logic circuit element, a graphical processing circuit element, an input/output circuit element, and a memory circuit element.

11. The method of claim 8 , wherein the second number is equal to one.

12. The method of claim 8 , wherein the recipient communication element connects the switching element and the recipient communication point, the recipient communication element including at least one through-silicon via.

13. The method of claim 8 , wherein a donor communication element connects the donor circuit block and the donor communication point, the donor communication element including at least one through-silicon via.

14. The method of claim 8 , wherein a chip connection element connects the recipient communication point and the donor communication point, the chip connection element created by at least one of wirebonding and soldering.

Assignees

• IBM

Inventors

• Bartley Gerald K
• Becker Darryl J
• Germann Philip R
• Hovis William P

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/092

  Adapting interconnections, e.g. making engineering charges, repairing · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title