Multiple active vertically aligned cores for three-dimensional chip stack

Patent metadata

Field	Value
Publication number	US-9310827-B2
Application number	US-201414278079-A
Country	US
Kind code	B2
Filing date	May 15, 2014
Priority date	Dec 5, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

An integrated circuit (IC) stack device for multiple active vertically stacked cores is disclosed. The IC stack device can include a primary IC having a first set of cores, and a supplementary IC interfaced with the primary IC having a second set of cores. The IC stack device can also include a peripheral component connection located such that the primary IC is between the peripheral component connection and the supplemental IC. The IC stack device can include control logic configured to route, in a primary mode, signals from a particular core of the first set of cores to a data bus. The control logic can route, in a secondary mode, signals from a particular core of the second set of cores to a data bus. The control logic can route, in a dual mode, signals from both of the particular cores to a data bus.

First claim

What is claimed is:

1. A method for operating an integrated circuit (IC) stack device, the method comprising:
enabling, on a first side of a primary IC, a set of first enabled cores;
disabling, on the first side of the primary IC, a set of first disabled cores;
enabling, on a first side of a secondary IC, a set of second enabled cores;
disabling, on the first side of the secondary IC, a set of second disabled cores having more cores than the set of first disabled cores,
adding a peripheral component connection to a location on the IC stack device such that the secondary IC is between the peripheral component connection and the primary IC, the peripheral component connection designed to electrically connect the IC stack device to one or more devices external to the IC stack device; and
selecting a mode for control logic that is designed to:
route, in a primary mode, signals from a particular enabled core of the first enabled cores to a data bus located within the IC stack device,
route, in a secondary mode, signals from a particular enabled core of the second enabled cores to a data bus located within the IC stack device, and
route, in a dual mode, signals from both of the particular enabled cores to a data bus located within the IC stack device.

2. The method of claim 1 , wherein the sets of cores include one or more microprocessors.

3. The method of claim 1 , further comprising setting, by a clock module connected to each respective core, a clock frequency based on factors related to efficiency and thermal management of the IC stack device, including a heat threshold and a power threshold.

4. The method of claim 3 , further comprising setting each core of the set of first enabled cores to a synchronous multiple of a first frequency.

5. The method of claim 3 , further comprising setting a particular core of the set of first enabled cores to a second frequency.

6. The method of claim 3 , further comprising setting each core of the set of second enabled cores to a synchronous multiple of a third frequency.

7. The method of claim 3 , further comprising setting a particular core of the set of second enabled cores to a fourth frequency.

8. The method of claim 1 , further comprising transferring, by a synchronous interface, of a clock frequency from a first clock domain to a second clock domain, the second clock domain an integer multiple of the first clock domain.

9. The method of claim 1 , further comprising transferring, by an asynchronous interface, of a clock frequency from a first clock domain to a second clock domain, the second clock domain asynchronous with the first clock domain.

Assignees

• IBM

Inventors

• Bartley Gerald K
• Becker Darryl J
• Hovis William P

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title