Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures

Patent metadata

Field	Value
Publication number	US-9608119-B2
Application number	US-71570410-A
Country	US
Kind code	B2
Filing date	Mar 2, 2010
Priority date	Mar 2, 2010
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.

First claim

What is claimed is:

1. A semiconductor device comprising:
an insulator material elevationally outward of and contacting first semiconductive material;
amorphous silicon elevationally outward of and contacting the insulator material;
a conductive material elevationally outward of and contacting the amorphous silicon, the conductive material being selected from the group consisting of a phase change material, titanium, titanium oxide, tantalum, tantalum oxide, tantalum nitride, and tungsten oxide;
second semiconductive material elevationally outward of the conductive material; and
a floating body memory cell comprising:
an active area comprising the second semiconductive material, insulating material on opposite sides of the active area;
a drain region and a source region within the second semiconductive material of the active area;
a first high-k dielectric material elevationally outward of and contacting the second semiconductive material of the active area between the drain region and the source region;
a transistor gate elevationally outward of and contacting the first high-k dielectric material;
a second high-k dielectric material elevationally between and contacting the conductive material and the second semiconductive material, the second high-k dielectric material contacting bottom surfaces of the drain region and the source region and of the second semiconductive material there-between, a bottom surface of the second high-k material contacting the conductive material along an entirety of a lateral width of the bottom surface; and
the conductive material extending laterally beyond lateral outermost edges of each of the drain region and the source region.

2. The semiconductor device of claim 1 wherein the transistor gate comprises metal.

3. The semiconductor device of claim 1 , wherein the amorphous silicon extends laterally beyond the lateral outermost edges of each of the drain region and the source region.

4. The semiconductor device of claim 1 , wherein the conductive material is elevationally between the insulating material that is on opposite sides of the active area and the amorphous silicon and extends along and contacts bottom surfaces of the insulating material that is on opposite sides of the active area.

5. A semiconductor-metal-on-insulator structure comprising:
a first wafer comprising an insulator material contacting semiconductive material;
a second wafer comprising amorphous silicon and semiconductive material, the second wafer comprising conductive material elevationally between the amorphous silicon and the semiconductive material of the second wafer, the conductive material being in direct contact with the amorphous silicon and being selected from the group consisting of a phase change material, titanium, titanium oxide, tantalum, tantalum oxide, tantalum nitride, and tungsten oxide;
the first and second wafers being adhered to one another with the amorphous silicon material of the second wafer and the insulator material of the first wafer contacting one another, the amorphous silicon being elevationally between the conductive material and the insulator material, the insulator material being elevationally between the semiconductive material of the first wafer and the amorphous silicon; and
a semiconductor device formed on or within the semiconductive material of the second wafer.

6. The semiconductor-metal-on-insulator structure of claim 5 , wherein the conductive material is a first conductive material and further comprising a second conductive material elevationally between the first conductive material and the semiconductive material of the second wafer.

7. The semiconductor-metal-on-insulator structure of claim 6 , wherein the second conductive material comprises titanium-rich titanium nitride in contact with the semiconductive material of the second substrate and tungsten silicide over the second semiconductive material.

8. The semiconductor-metal-on-insulator structure of claim 6 , wherein the first conductive material comprises a metal other than titanium and a titanium material.

9. The semiconductor-metal-on-insulator structure of claim 8 , wherein the metal other than titanium is tungsten.

10. The semiconductor-metal-on-insulator structure of claim 8 , wherein the metal other than titanium is aluminum.

11. The semiconductor-metal-on-insulator structure of claim 5 , wherein the first and second wafers are each a full and unpatterned wafer.

12. A semiconductor device comprising:
an insulator material elevationally outward of and contacting first semiconductive material;
amorphous silicon elevationally outward of and contacting the insulator material;
a conductive material elevationally outward of and contacting the amorphous silicon, the conductive material being selected from the group consisting of a phase change material, titanium, titanium oxide, tantalum, tantalum oxide, tantalum nitride, and tungsten oxide;
second semiconductive material elevationally outward of the conductive material; and
a floating body memory cell comprising:
an active area comprising the second semiconductive material, insulating material on opposite sides of the active area;
a drain region and a source region within the second semiconductive material of the active area;
a first high-k dielectric material elevationally outward of and contacting the second semiconductive material of the active area between the drain region and the source region;
a transistor gate elevationally outward of and contacting the first high-k dielectric material;
a second high-k dielectric material elevationally between and contacting the conductive material and the second semiconductive material, the second high-k dielectric material contacting bottom surfaces of the drain region and the source region and of the second semiconductive material there-between, a bottom surface of the second high-k material contacting the conductive material along an entirety of a lateral width of the bottom surface; and
the amorphous silicon extending laterally beyond lateral outermost edges of each of the drain region and the source region.

13. The semiconductor device of claim 12 , wherein the conductive material is elevationally between the insulating material that is on opposite sides of the active area and the amorphous silicon and extends along and contacts bottom surfaces of the insulating material that is on opposite sides of the active area.

14. A semiconductor device comprising:
an insulator material elevationally outward of and contacting first semiconductive material;
amorphous silicon elevationally outward of and contacting the insulator material;
a conductive material elevationally outward of and contacting the amorphous silicon, the conductive material being selected from the group consisting of a phase change material, titanium, titanium oxide, tantalum, tantalum oxide, tantalum nitride, tungsten, tungsten silicide, and tungsten oxide;
second semiconductive material elevationally outward of the conductive material; and
a floating body memory cell comprising:
an active area comprising the second semiconductive material, insulating material on opposite sides of the active area;
a drain region and a source region within the second semiconductive material of the active area;
a first high-k dielectric material elevationally outward of and contacting the second semiconductive material of the active area between the drain region and the source region;
a transistor gate elevationally outward of and contacting the first high-k dielectric material;
a second high-k dielectric material elevationally between and contacting the

Assignees

• Tang Sanh D
• Zhang Ming
• Bayless Andrew M
• Zahurak John K
• Micron Technology Inc

Inventors

• Tang Sanh D
• Zhang Ming
• Bayless Andrew M
• Zahurak John K

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P90/1914 Primary

  using bonding · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3454

  Amorphous · CPC title