Method of making a finFET, and finFET formed by the method

Patent metadata

Field	Value
Publication number	US-9312179-B2
Application number	US-72555410-A
Country	US
Kind code	B2
Filing date	Mar 17, 2010
Priority date	Mar 17, 2010
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

First claim

What is claimed is:

1. A method comprising:
forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region comprising an STI material therebetween, a first distance between a topmost surface of the STI region and a top surface of the first fin, and a second distance between the topmost surface of the STI region and a top surface of the second fin;
providing a first fin extension on top and side surfaces of the first fin entirely above the topmost surface of the STI region at a time the first fin extension is formed, wherein the first fin extension does not extend below a topmost surface of the STI material at the time the first fin extension is formed, and providing a second fin extension on top and side surfaces of the second fin entirely above the topmost surface of the STI region at a time the second fin extension is formed, wherein the second fin extension does not extend below the topmost surface of the STI material at the time the second fin extension is formed; and then
removing STI material from the STI region, so as to increase the distance between the topmost surface of the STI material and the top surface of the first fin and increase the distance between the topmost surface of the STI material and the top surface of the second fin;
depositing a conformal stressor dielectric material over the fins and STI region;
reflowing the conformal stressor dielectric material to flow into a space between the first and second fins above a topmost surface of the STI region, to apply stress to a channel of the finFET.

2. The method of claim 1 , wherein the depositing step includes depositing the conformal stressor dielectric material over a gate electrode of the finFET.

3. The method of claim 2 , wherein the reflowing step leaves a film of the conformal stressor dielectric material adjacent the gate electrode to form sidewall spacers.

4. The method of claim 3 , further comprising performing source and drain dopant implantation after forming the sidewall spacers.

5. The method of claim 1 , wherein the conformal stressor dielectric material is a silicon nitride film deposited by plasma enhanced chemical vapor deposition.

6. The method of claim 1 , wherein the conformal stressor dielectric material is a silicon nitride film deposited by plasma enhanced atomic layer deposition.

7. The method of claim 1 , wherein the step of providing first and second fin extensions comprises depositing an SiGe film over the top and side surfaces of the first and second fins.

8. The method of claim 1 , wherein the step of removing material includes lowering the top surface of the STI region by a distance below bottoms of the fin extensions.

9. The method of claim 8 , wherein the reflowing step includes flowing the stressor material into the space above the STI region to a non-zero height above the bottoms of the fin extensions.

10. The method of claim 1 , wherein the conformal stressor dielectric material applies a compressive stress of about 1 GPa to about 3GPa to a contact etch stop layer over the fin extensions.

11. The method of claim 6 , wherein the conformal stressor dielectric material applies a compressive stress of about 1.5 GPa to about 3GPa to a contact etch stop layer over the fin extensions.

12. The method of claim 1 , wherein the removing step includes dipping the substrate in hydrogen fluoride.

13. A method comprising:
providing first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region comprising an STI material therebetween, a first distance between a topmost surface of the STI region and a top surface of the first fin and a second distance between the topmost surface of the STI region and a top surface of the second fin;
forming a gate electrode over the first and second fins;
forming a first SiGe fin extension on top and side surfaces of the first fin entirely above the topmost surface of the STI region at a time the first SiGe fin extension is formed, wherein the first SiGe fin extension does not extend below a topmost surface of the STI material at the time the first SiGe fin extension is formed, and forming a second SiGe fin extension on top and side surfaces of the second fin entirely above the topmost surface of the STI region at a time the second SiGe fin extension is formed, wherein the second SiGe fin extension does not extend below a topmost surface of the STI material at the time the second SiGe fin extension is formed; and then
removing STI material from the STI region, so as to increase the distance between the topmost surface of the STI material and the top surface of the first fin and the second distance between the topmost surface of the STI material and the top surface of the second fin;
depositing a conformal stressor dielectric material over the fins, the gate electrode and the STI region;
reflowing the conformal stressor dielectric material to flow into a space defined between the first and second fins above a topmost surface of the STI region, to apply stress to a channel region of the finFET, while leaving a film of the conformal stressor dielectric material adjacent the gate electrode to form sidewall spacers; and
implanting source and drain regions after the reflowing.

14. The method of claim 13 , wherein the step of removing material includes lowering the top surface of the STI region by a distance below bottoms of the fin extensions.

15. The method of claim 14 , wherein the reflowing step includes flowing the conformal stressor dielectric material into the space above the STI region until the conformal stressor dielectric material has a non-zero height above the bottoms of the fin extensions.

16. The method of claim 13 , wherein the conformal stressor dielectric material applies a compressive stress of about 1.5 GPa to about 3GPa to a contact etch stop layer over the fin extensions.

17. The method of claim 1 , wherein the topmost surface of the STI material extends to contact a side of the first fin and a side of the second fin throughout a period when the first fin extension and second fin extension are being formed.

18. The method of claim 13 , wherein the topmost surface of the STI material extends to contact a side of the first fin and a side of the second fin throughout a period when the first SiGe fin extension and second SiGe fin extension are being formed.

19. A method comprising:
forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region comprising an STI material therebetween, a first distance of about 80 nm to about 85 nm between a topmost surface of the STI region and a top surface of the first fin, and a second distance of about 80 nm to about 85 nm between the topmost surface of the STI region and a top surface of the second fin;
providing a first fin extension on top and side surfaces of the first fin entirely above the topmost surface of the STI region at a time the first fin extension is formed, wherein the first fin extension does not extend below a topmost surface of the STI material at the time the first fin extension is formed, and providing a second fin extension on top and side surfaces of the second fin entirely above the top surface of the STI region at a time the second fin extension is formed, wherein the second fin extension does not extend below the top surface of the STI material at the time the second fin extension is formed; and then
removing STI material from the STI region, so as to inc

Assignees

• Lin Chia-Pin
• Chan Chien-Tai
• Lin Hsien-Chin
• Lin Shyue-Shyh
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chia-Pin
• Chan Chien-Tai
• Lin Hsien-Chin
• Lin Shyue-Shyh

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/792

  comprising applied insulating layers, e.g. stress liners · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/0193

  the components including FinFETs · CPC title