Self aligned epitaxial based punch through control

Patent metadata

Field	Value
Publication number	US-9608069-B1
Application number	US-201615097741-A
Country	US
Kind code	B1
Filing date	Apr 13, 2016
Priority date	Apr 13, 2016
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method of forming a semiconductor device that may include etching source and drain portions of a fin structure of a first semiconductor material selectively to an underlying semiconductor layer of a second semiconductor material, and laterally etching undercut region in the semiconductor layer underlying the fin structure. The method may further include filling the undercut region with a first conductivity type semiconductor material, and forming a second conductivity type semiconductor material for a source region and a drain region on opposing sides of the channel region portion of the fin structure.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
etching source and drain portions of a fin structure of a first semiconductor material selectively to an underlying semiconductor layer of a second semiconductor material, wherein the source and drain region portions are on opposing sides of a channel region portion of the fin structure;
laterally etching undercut region in the semiconductor layer underlying the fin structure;
filling the undercut region with a first conductivity type semiconductor material; and
forming a second conductivity type semiconductor material for a source region and a drain region on opposing sides of the channel region portion of the fin structure.

2. The method of claim 1 , wherein the first semiconductor material comprises silicon and the second semiconductor material comprises silicon germanium.

3. The method of claim 1 further comprising forming a gate structure on the channel region portion of the fin structure.

4. The method of claim 3 , wherein following said etching, a sidewall of the fin structure is aligned with gate sidewall of said gate structure.

5. The method of claim 1 , wherein said etching said source and drain portions of the silicon containing fin structure comprises an isotropic etch.

6. The method of claim 1 , wherein said filling the undercut region with the first conductivity type semiconductor material comprises epitaxial growth.

7. The method of claim 6 , wherein a portion of the first conductivity type semiconductor material is epitaxially grown on the sidewall of the fin structure, wherein said method further comprises applying a wet etch to remove said portion of the first conductivity type semiconductor material formed on said sidewall of the fin structure.

8. The method of claim 1 , further comprising a drive in anneal following formation of the first conductivity type semiconductor material.

9. The method of claim 1 further comprising forming an epitaxial buffer layer on an upper surface of said first conductivity type semiconductor material, and on said sidewalls of the fin structure, wherein the epitaxial buffer layer comprises said second conductivity.

10. The method of claim 9 , wherein forming the forming of the second conductivity type semiconductor material for the source region and the drain region on opposing sides of the channel region portion of the fin structure comprises epitaxial growth on the epitaxial buffer layer, wherein a dopant concentration that dictates the second conductivity type in the epitaxial buffer layer is greater than a dopant concentration that dictates the second conductivity type in the source region and drain region.

11. A method of forming a semiconductor device comprising:
forming a gate structure on a channel portion of a silicon containing fin structure;
removing a portion of the silicon containing fin structure extending past said channel portion on opposing sides of said gate structure selectively to an underlying germanium containing layer;
laterally etching undercut region in the germanium containing layer underlying the silicon containing fin structure;
filling the undercut region with a first conductivity type semiconductor material; and
forming a second conductivity type semiconductor material for a source region and a drain region on opposing sides of the channel region portion of the fin structure.

12. The method of claim 11 , wherein the gate structure formed prior to removing said portion of the silicon containing fin structure is a sacrificial gate structure that is replaced with a functional gate structure after forming the second conductivity type semiconductor material for the source region and the drain region.

13. A semiconductor device comprising:
a gate structure present on a channel region of a fin structure, wherein the fin structure is composed of a first semiconductor material type and is present atop a semiconductor layer of a second semiconductor material type having a first concentration of a first conductivity type dopant;
a punch through stop region comprising said second semiconductor material type and having said first conductivity type dopant in a concentration greater than the first conductivity type dopant in the semiconductor layer, wherein said punch through stop region is composed of epitaxial material filling an undercut region extending into the semiconductor material underlying the fin structure; and
source and drain regions composed of epitaxial semiconductor material of said first semiconductor material type is present on opposing sides of said channel region and atop said punch through stop region, the source and drain regions doped to a second conductivity type.

14. The semiconductor device of claim 13 , wherein a buffer layer of said first semiconductor material type and having the second conductivity type is present on a upper portion of the punch through stop region and a sidewall of the fin structure on opposing sides of the gate structure.

15. The semiconductor device of claim 14 , wherein a dopant concentration for provided said second conductivity type in said buffer layer is greater than a dopant concentration for providing said second conductivity type in said source and drain regions.

16. The semiconductor device of claim 15 , wherein a dopant concentration that provides the first conductivity type for the punch through stop region is greater than a dopant concentration that provides the first conductivity type of the semiconductor layer.

17. The semiconductor device of claim 16 , wherein the punch through stop region is present extending beneath the fin structure underlying the gate structure on both sides of the gate structure, but the opposing portions of the punch through stop region do not extend across an entirety of a width of the semiconductor layer underlying the gate structure.

18. The semiconductor device of claim 17 , wherein the first semiconductor material type is silicon and the second semiconductor material type is silicon germanium.

19. The semiconductor device of claim 18 , wherein the first semiconductor material type for the buffer layer further comprise carbon.

20. The semiconductor device of claim 19 , wherein the first conductivity type is a p-type conductivity, and the second conductivity type is an n-type conductivity.

Assignees

• IBM
• Intenational Business Machines Corp

Inventors

• Basker Veeraraghavan S
• Liu Zuoguang
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D62/371 Primary

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title

• H01L27/0924

  Electricity · mapped topic

• H01L29/66636

  Electricity · mapped topic