Multi-layered printed circuit board having inner-layer portion and outer-layer portions and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9603265-B2
Application number	US-201514705586-A
Country	US
Kind code	B2
Filing date	May 6, 2015
Priority date	Jul 8, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A multi-layered printed circuit board and a manufacturing method thereof are disclosed. The multi-layered printed circuit board in accordance with an aspect of the present invention includes: an inner-layer portion having an inner-layer wired pattern formed thereon; outer-layer portions having inner-layer wired portions formed thereon and being laminated on either surface of the inner-layer portion; a first via-hole formed to penetrate one of the outer-layer portions so as to be connected to a first point of the inner-layer wired pattern; and a second via-hole formed to penetrate the other of the outer-layer portions so as to be connected with a second point of the inner-layer wired pattern. The second via-hole is formed in an area of the inner-layer portion and the outer-layer portions that is removed through external form processing.

First claim

What is claimed is:

1. A multi-layered printed circuit board comprising:
an inner-layer portion having an inner-layer wired pattern formed thereon;
outer-layer portions having outer-layer wired patterns formed thereon and being laminated on either surface of the inner-layer portion;
a first via-hole formed to penetrate one of the outer-layer portions so as to be connected to a first point of the inner-layer wired pattern; and
a second via-hole formed to penetrate the one of the outer-layer portions so as to be connected with a second point of the inner-layer wired pattern,
wherein the second via-hole is formed in an area of the inner-layer portion and the outer-layer portions that is subsequently removed through external form processing.

2. The multi-layered printed circuit board of claim 1 , further comprising prepreg layers interposed between the inner-portion layer and the outer-portion layers so as to insulate the inner-portion layer from the outer-portion layers.

3. The multi-layered printed circuit board of claim 1 , wherein the inner-layer wired pattern has open-circuit thereof measured through an electrical test between the first via-hole and the second via-hole.

4. A method of manufacturing a multi-layered printed circuit board, comprising:
forming an inner-layer wired pattern on an inner-layer portion;
laminating outer-layer portions on either surface of the inner-layer portion;
forming a first via-hole to penetrate one of the outer-layer portions so as to be connected with a first point of the inner-layer wired pattern;
forming a second via-hole to penetrate the one of the outer-layer portions so as to be connected with a second point of the inner-layer wired pattern;
plating insides of the first via-hole and the second via-hole;
forming outer-layer wired patterns on the outer-layer portions; and
removing the second via-hole and an area of the inner-layer portion and the outer-layer portion surrounding the second via-hole.

5. The method of claim 4 , further comprising laminating prepreg layers on either surface of the inner-layer portion, prior to the laminating of the outer-layer portions.

6. The method of claim 4 , further comprising conducting an electrical test between the first via-hole and the second via-hole, after the forming of the outer-layer wired patterns.

7. The method of claim 6 , the removing of the second via-hole and the area of the inner-layer portion and the outer layer portion surrounding the second via-hole is performed after the conducting of the electrical test.

8. The multi-layered printed circuit board of claim 2 , wherein the inner-layer wired pattern has open-circuit thereof measured through an electrical test between the first via-hole and the second via-hole.

9. The method of claim 5 , further comprising conducting an electrical test between the first via-hole and the second via-hole, after the forming of the outer-layer wired patterns.

Assignees

• Samsung Electro Mech

Inventors

• Lee Ji-Won
• Kim Jin-Kyu

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title