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US-2024215150-A1 · Jun 27, 2024 · US
Method for manufacturing printed circuit board
US9107329B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9107329-B2 |
| Application number | US-201113232220-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 14, 2011 |
| Priority date | May 11, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
Disclosed herein is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes: preparing a base substrate having first connection pads and second connection pads; forming a solder resist layer on the base substrate, the solder resist layer having a first opening for exposing the first connection pads; forming a first surface treatment layer on the first connection pads; forming a protective film on the solder resist layer; forming a second opening for exposing the second connection pads in the protective film and the solder resist layer; and forming a second surface treatment layer on the second connection pads.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a printed circuit board, the method comprising the following steps in sequence: preparing a base substrate having first connection pads and second connection pads; forming a solder resist layer on the base substrate, the solder resist layer having a first opening for exposing the first connection pads; forming a first surface treatment layer on the first connection pads; forming a protective film on the solder resist layer;…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9107329B2 cover?
- Disclosed herein is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes: preparing a base substrate having first connection pads and second connection pads; forming a solder resist layer on the base substrate, the solder resist layer having a first opening for exposing the first connection pads; forming a first surface treatment laye…
- Who is the assignee on this patent?
- Lee Chang Bo, Hong Dae Jo, Choi Cheol Ho, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H05K3/243. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).