Manufacturing method for multi-layer circuit board

US9095083B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9095083-B2
Application numberUS-201314074655-A
CountryUS
Kind codeB2
Filing dateNov 7, 2013
Priority dateNov 7, 2013
Publication dateJul 28, 2015
Grant dateJul 28, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A manufacturing method for a multi-layer circuit board includes the following steps. Firstly, a substrate having a first via penetrating the substrate is provided. Next, a patterned circuit layer is formed on a surface of the substrate by using the first via as an alignment target. The first patterned circuit layer includes a first concentric-circle pattern surrounding the first via. Next, a first stacking layer is formed on the surface. Then, a first through hole penetrating regions where a first concentric circle from the center of the concentric-circle pattern is orthogonally projected on the first stacking layer and the substrate is formed. Next, a second stacking layer is formed on the first stacking layer. Afterward, a second through hole penetrating regions where a second concentric circle from the center of the concentric-circle pattern is orthogonally projected on of the first, the second stacking layers and the substrate is formed.

First claim

Opening claim text (preview).

What is claimed is: 1. A manufacturing method for a multi-layer circuit board, comprising: providing a substrate having a first via penetrating the substrate; forming a first patterned circuit layer on a surface of the substrate by using the first via as an alignment target, and the first patterned circuit layer including a first concentric-circle pattern surrounding the first via; forming a first stacking layer on the surface and covering the first patterned circuit layer, an…

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What does patent US9095083B2 cover?
A manufacturing method for a multi-layer circuit board includes the following steps. Firstly, a substrate having a first via penetrating the substrate is provided. Next, a patterned circuit layer is formed on a surface of the substrate by using the first via as an alignment target. The first patterned circuit layer includes a first concentric-circle pattern surrounding the first via. Next, a fi…
Who is the assignee on this patent?
Unimicron Technology Corp
What technology area does this patent fall under?
Primary CPC classification H05K1/0298. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 28 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).