Method and circuit configuration for determining position minus time

Patent metadata

Field	Value
Publication number	US-9602109-B2
Application number	US-201113637113-A
Country	US
Kind code	B2
Filing date	Mar 16, 2011
Priority date	Mar 31, 2010
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.

First claim

What is claimed is:

1. A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out, wherein the prediction is dependent on at least one input signal, a predefined first time value and at least one predefined first physical value which represents another physical variable, comprising:
a processing device of the data processing system, wherein upon each change of the at least one input signal, the processing device of the data processing system performs:
calculating a second time value from the predefined first physical value with the aid of at least one of an instantaneous time and another state parameter,
at least one of (i) subtracting the predefined first time value from the second time value to form a third time value, and (ii) calculating a second physical value from the first time value,
subtracting the first physical value from the second physical value to form a third physical value;
determining, based on at least one of the third time value and the third physical value, a state in which the at least one operation is to be triggered; and
transmitting the state to a unit that triggers the at least one operation based on the transmitted state;
wherein the processing device includes:
a multichannel sequencer which identifies the each change of the at least one input signal and transmits, upon identification of the each change, the predefined first time value, the instantaneous time, and the another state parameter; and
a digital phase locked loop which:
receives the predefined first time value, the instantaneous time, and the another state parameter from the multichannel sequencer,
receives the at least one input signal from a sensor associated with a component generating the at least one input signal,
calculates the second time value,
at least one of: (i) subtracts the predefined first time value from the second time value to form the third time value, and (ii) calculates the second physical value from the first time value,
subtracts the first physical value from the second physical value to form the third physical value, and
transmits at least one of the third time value and the third physical value.

2. The circuit configuration as recited in claim 1 , wherein:
the output unit includes a control bit;
a comparison unit is configured to carry out a comparison of the at least one predefined first physical value to a reference value for the another physical variable; and
the output unit is configured to switch over, as a function of the control bit, the comparison unit between (i) a first comparison mode in which greater-than-or-equal-to relationship is tested, and (ii) a second comparison mode in which less-than-or-equal-to relationship is tested.

3. The circuit configuration as recited in claim 1 , wherein the processing device further includes:
an output unit which:
receives the at least one of the third time value and the third physical value from the digital phase lock loop,
determines the state in which the at least one operation is to be triggered, and
transmits the state to at least one of the unit that triggers the at least one operation and a communicatively coupled central processing unit (CPU).

4. The circuit configuration as recited in claim 3 , wherein the output unit is configured as an advanced timer output module, and wherein the advanced timer output module continuously requests that the digital phase lock loop recalculates at least one of the third time value and the third physical value.

5. A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out, wherein the prediction is dependent on at least one input signal, a predefined first time value and at least one predefined first physical value which represents another physical variable, comprising:
a processing device of the data processing system, wherein upon each change of the at least one input signal, the processing device of the data processing system performs:
calculating a second time value from the predefined first physical value with the aid of at least one of an instantaneous time and another state parameter,
at least one of (i) subtracting the predefined first time value from the second time value to form a third time value, and (ii) calculating a second physical value from the first time value,
subtracting the first physical value from the second physical value to form a third physical value;
determining, based on at least one of the third time value and the third physical value, a state in which the at least one operation is to be triggered; and
transmitting the state to a unit that triggers the at least one operation based on the transmitted state;
wherein the circuit configuration is further configured to: (a) determine one of (i) the third physical value from the third time value, or (ii) the third time value from the third physical value, and (b) relay at least one of the third time value or third physical value to an output unit;
wherein the output unit is configured to perform the following: (a) at least one of (i) comparing the third time value to a reference time base value, and (ii) comparing the third physical value to a reference physical value; and (b) changing an output signal as a function of at least one of the comparisons;
wherein the processing device includes:
a multichannel sequencer which identifies the each change of the at least one input signal and transmits, upon identification of the each change, the predefined first time value, the instantaneous time, and the another state parameter;
a digital phase locked loop which:
receives the predefined first time value, the instantaneous time, and the another state parameter from the multichannel sequencer,
receives the at least one input signal from a sensor associated with a component generating the at least one input signal,
calculates the second time value,
at least one of: (i) subtracts the predefined first time value from the second time value to form the third time value, and (ii) calculates the second physical value from the first time value,
subtracts the first physical value from the second physical value to form the third physical value, and
transmits at least one of the third time value and the third physical value; and

an output unit which:
receives the at least one of the third time value and the third physical value from the digital phase lock loop,
determines the state in which the at least one operation is to be triggered, and
transmits the state to at least one of the unit that triggers the at least one operation and a communicatively coupled central processing unit (CPU).

6. The circuit configuration as recited in claim 5 , wherein the circuit configuration is further configured to transfer at least one of a fourth time value and a fourth physical value to the output unit so that at least one of the fourth time value and the fourth physical value is taken into consideration for changing the output signal.

7. The circuit configuration as recited in claim 6 , wherein the circuit configuration is further configured to transfer at least one additional control signal to the output unit, and wherein the at least one additional control signal dictates which of the third time value, the third physical value, the fourth time value or the fourth physical value is to be compared to a respective reference value.

8. The circuit configuration as recited in claim 7 , wherein the output unit is further configured to output a status signal which provides information about which of the third time value, the third physical value, the fourth time value or the fourth physical value is to be compared to a respective refer

Assignees

• Boehl Eberhard
• Hempel Andreas
• Thoss Dieter
• Bartholomae Ruben
• Schmitt Stephen
• Merker Andreas
• Bosch Gmbh Robert

Inventors

• Boehl Eberhard
• Hempel Andreas
• Thoss Dieter
• Bartholomae Ruben
• Schmitt Stephen
• Merker Andreas

Classifications

• F02D41/401

  Controlling injection timing (F02D41/402 takes precedence) · CPC title

• H03K99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• F02D41/0097

  using means for generating speed signals · CPC title

• G05B2219/2623

  Combustion motor · CPC title

• G05B13/026 Primary

  using a predictor · CPC title