Semiconductor device having stacked chips

Patent metadata

Field	Value
Publication number	US-10157894-B2
Application number	US-201715819468-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Sep 6, 2012
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A semiconductor device includes a first chip having a first via and a second via through the first chip; and a second chip provided on the first chip and having a third via and a fourth via through the second chip. The first chip includes: a first logical operation circuit configured to perform a first logical operation (NOT) on a first address input signal to output a first address output signal to the second chip through the first via; a second logical operation circuit connected to the first logical operation circuit, the second logical operation circuit being configured to perform a second logical operation (XOR) on a second address input signal and the first address output signal to output a second address output signal to the second chip through the second via; and a first activation circuit connected to the second logical operation circuit, the first activation circuit being configured to activate the first chip based on at least the second address output signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first chip having a first via and a second via through the first chip; and
a second chip provided on the first chip and having a third via and a fourth via through the second chip;
wherein the first chip includes:
a first logical operation circuit configured to perform a first logical operation (NOT) on a first address input signal to output a first address output signal to the second chip through the first via;
a second logical operation circuit connected to the first logical operation circuit, the second logical operation circuit being configured to perform a second logical operation (XOR) on a second address input signal and the first address output signal to output a second address output signal to the second chip through the second via; and
a first activation circuit connected to the second logical operation circuit, the first activation circuit being configured to activate the first chip based on at least the second address output signal.

2. The device according to claim 1 , further comprising:
a third chip provided on the second chip,
wherein the second chip includes:
a third logical operation circuit configured to perform the first logical operation (NOT) on the first address output signal to output a third address output signal to the third chip through the third via;
a fourth logical operation circuit connected to the third logical operation circuit, the fourth logical operation circuit being configured to perform the second logical operation (XOR) on the second address output signal and the third address output signal to output a fourth address output signal to the third chip through the fourth via; and
a second activation circuit connected to the fourth logical operation circuit, the second activation circuit being configured to activate the second chip based on at least the fourth address output signal.

3. The device according to claim 2 , wherein:
the first chip has a fifth via and a sixth via through the first chip,
the second chip has a seventh via and an eighth via through the second chip, the seventh via being connected to the fifth via and the eighth via being connected to the sixth via,
the fifth and seventh vias are configured to transmit a first chip enable signal therethrough, and
the sixth and eighth vias are configured to transmit a second chip enable signal therethrough.

4. The device according to claim 3 ,
wherein the first activation circuit of the first chip is configured to activate the first chip based on the second address output signal, the first chip enable signal and second chip enable signal, and
the second activation circuit of the second chip is configured to activate the second chip based on the fourth address output signal, the first chip enable signal and second chip enable signal.

5. The device according to claim 1 ,
wherein the first logical operation (NOT) is an inversion operation, and
the second logical operation (XOR) is an exclusive disjunction operation.

6. A method for controlling a semiconductor device,
the semiconductor device comprising:
a first chip having a first via and a second via through the first chip; and
a second chip provided on the first chip and having a third via and a fourth via through the second chip;

the method including:
in the first chip, performing a first logical operation (NOT) on a first address input signal to output a first address output signal to the second chip through the first via;
in the first chip, performing a second logical operation (XOR) on a second address input signal and the first address output signal to output a second address signal to the second chip through the second via; and
in the first chip, activating the first chip based on at least the second address output signal.

7. The method according to claim 6 , further comprising:
in the second chip, performing the first logical operation (NOT) on the first address input signal to output a third address output signal to a third chip through the third via;
in the second chip, performing the second logical operation (XOR) on the second address output signal and the third address output signal to output a fourth address output signal to the third chip through the fourth via; and
in the second chip, activating the second chip based on at least the fourth address output signal.

8. The method according to claim 7 , wherein:
the first chip has a fifth via and a sixth via through the first chip,
the second chip has a seventh via and an eighth via through the second chip, the seventh via being connected to the fifth via and the eighth via being connected to the sixth via,
the method further comprising:
transmitting a first chip enable signal through the fifth and seventh vias; and
transmitting a second chip enable signal (S 62 ) through the sixth and eighth vias.

9. The method according to claim 8 ,
wherein the first chip is activated based on the second address output signal, the first chip enable signal and second chip enable signal, and
the second chip is activated based on the fourth address output signal, the first chip enable signal and second chip enable signal.

10. The method according to claim 6 ,
wherein the first logical operation (NOT) is an inversion operation, and
the second logical operation (XOR) is an exclusive disjunction operation.

Assignees

• Toshiba Memory Corp

Inventors

• Koyanagi Masaru

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/859

  Bump connectors and bond wires · CPC title