FinFET structures having silicon germanium and silicon channels

Patent metadata

Field	Value
Publication number	US-9589848-B2
Application number	US-201514678024-A
Country	US
Kind code	B2
Filing date	Apr 3, 2015
Priority date	Jul 24, 2013
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

First claim

What is claimed is:

1. A method comprising:
forming a patterned mandrel layer on a semiconductor substrate, the patterned mandrel layer including mandrel portions having side walls;
recessing one or more portions of the semiconductor substrate to form one or more trenches within the semiconductor substrate;
epitaxially growing a silicon germanium layer within the one or more trenches;
forming spacers on the side walls of the mandrel portions;
removing the mandrel portions from the semiconductor substrate;
removing portions of the semiconductor substrate and the silicon germanium layer between the spacers, thereby forming a first plurality of parallel fins from the semiconductor substrate and a second plurality of parallel fins from the silicon germanium layer;
forming a mask over a selected region of the semiconductor substrate and selected mandrel portions in the selected region of the semiconductor substrate prior to recessing the one or more portions of the semiconductor substrate; and
removing the mask following the step of epitaxially growing the silicon germanium layer, wherein the semiconductor substrate comprises a bulk silicon substrate.

2. The method of claim 1 , further including a step of forming n-type FinFET devices using the first plurality of fins and p-type FinFET devices using the second plurality of fins formed from the silicon germanium layer.

3. The method of claim 2 , wherein the step of forming the patterned mandrel layer further includes forming equally spaced mandrel portions of equal width.

4. The method of claim 1 , wherein both the first and second plurality of fins have heights of less than fifty nanometers.

5. The method of claim 1 , wherein the step of removing portions of the semiconductor substrate and the silicon germanium layer between the spacers includes performing a reactive ion etch.

6. The method of claim 1 , wherein the step of forming the first plurality of fins from the semiconductor substrate and the second plurality of fins from the silicon germanium layer further includes forming at least one fin comprising silicon germanium parallel to and within less than 30 nm of one of the first plurality of fins formed from the semiconductor substrate.

7. The method of claim 6 , wherein the silicon germanium layer has a germanium atomic concentration of ten to sixty percent.

8. A method comprising:
forming a patterned mandrel layer on a semiconductor substrate, the patterned mandrel layer including mandrel portions having side walls;
recessing one or more portions of the semiconductor substrate to form one or more trenches within the semiconductor substrate;
epitaxially growing a silicon germanium layer within the one or more trenches;
forming spacers on the side walls of the mandrel portions;
removing the mandrel portions from the semiconductor substrate;
removing portions of the semiconductor substrate and the silicon germanium layer between the spacers, thereby forming a first plurality of parallel fins from the semiconductor substrate and a second plurality of parallel fins from the silicon germanium layer; and
forming a mask on a portion of the semiconductor substrate, a portion of the silicon germanium layer adjoining the semiconductor substrate, and a plurality of the spacers prior to forming both the first and second plurality of fins, wherein the semiconductor substrate comprises a bulk silicon substrate.

9. The method of claim 8 , further including the step of forming n-type FinFET devices using the first plurality of fins and p-type FinFET devices using the second plurality of fins formed from the silicon germanium layer.

Assignees

• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Khakifirooz Ali
• Reznicek Alexander
• Shahidi Ghavam G

Classifications

• H10P76/40

  of masks comprising inorganic materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title