Substrate, chip arrangement, and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9585241-B2
Application number	US-201314034669-A
Country	US
Kind code	B2
Filing date	Sep 24, 2013
Priority date	Sep 24, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

In various embodiments, a substrate is provided. The substrate may include: a ceramic carrier having a first side and a second side opposite the first side; a first metal layer disposed over the first side of the ceramic carrier; a second metal layer disposed over the second side of the ceramic carrier; and a cooling structure formed into or over the second metal layer.

First claim

What is claimed is:

1. A chip arrangement comprising:
a first substrate, comprising:
a ceramic carrier comprising a first side and a second side opposite the first side;
a first metal layer disposed over the first side of the ceramic carrier;
a second metal layer disposed over the second side of the ceramic carrier;
a cooling structure formed into or over the second metal layer; wherein the cooling structure is formed from the same metal as the second metal layer;
wherein the cooling structure is configured to form a structure selected from a group consisting of a pin structure, a fin structure, and combinations thereof;

a chip disposed on the first metal layer of the first side of the first substrate, wherein the chip is electrically coupled to the first metal layer of the first substrate; and
a second substrate, comprising:
a ceramic carrier comprising a first side and a second side opposite the first side;
a first metal layer disposed over the first side of the ceramic carrier;
a second metal layer disposed over the second side of the ceramic carrier; and
a cooling structure formed into or over the second metal layer; wherein the cooling structure is formed from the same metal as the second metal layer;

wherein the chip is sandwiched between the first substrate and the second substrate and furthermore directly coupled to the second substrate, wherein the chip is furthermore electrically coupled to the first metal layer of the second substrate.

2. The chip arrangement of claim 1 , further comprising:
encapsulation material disposed at least partially over the sidewalls of the chip and at least one of the first substrate and/or the second substrate.

3. The chip arrangement of claim 1 , further comprising:
encapsulation material disposed at least partially over the sidewalls of the chip and the first substrate and the second substrate.

4. The chip arrangement of claim 3 ,
wherein the second metal layer of the first substrate and the second metal layer of the second substrate are at least partially exposed.

5. The chip arrangement of claim 1 ,
wherein the ceramic carrier comprises at least one metal oxide or metal nitride;
and wherein the first metal layer and the second metal layer comprise copper.

6. The chip arrangement of claim 1 ,
wherein the ceramic carrier of the first substrate and/or the ceramic carrier of the second substrate comprise at least one metal oxide or metal nitride; and
wherein the first metal layer and the second metal layer comprise copper.

7. The chip arrangement of claim 1 , wherein the second metal layer and the cooling structure are formed of a single, continuous piece of material.

8. The chip arrangement of claim 1 , wherein the first metal layer is formed from the same metal as the second metal layer.

9. A chip arrangement comprising:
a first substrate, comprising:
a ceramic carrier comprising a first side and a second side opposite the first side;
a first metal layer disposed over the first side of the ceramic carrier;
a second metal layer disposed over the second side of the ceramic carrier;
a cooling structure formed into or over the second metal layer; wherein the cooling structure is formed from the same metal as the second metal layer;
wherein the cooling structure is configured to form a structure selected from a group consisting of a pin structure, a fin structure, and combinations thereof;

a chip disposed on the first metal layer of the first side of the first substrate, wherein the chip is electrically coupled to the first metal layer of the first substrate; and
a second substrate, comprising:
a ceramic carrier comprising a first side and a second side opposite the first side;
a first metal layer disposed over the first side of the ceramic carrier;
a second metal layer disposed over the second side of the ceramic carrier; and
a cooling structure formed into or over the second metal layer; wherein the cooling structure is formed from the same metal as the second metal layer;

wherein the chip is sandwiched between the first substrate and the second substrate and furthermore coupled to the second substrate, wherein the chip is furthermore electrically coupled to the first metal layer of the second substrate; and wherein the chip arrangement is configured to have a cooling fluid applied to all sides of the chip arrangement.

10. A method for forming a chip arrangement, comprising:
forming a first substrate, comprising:
forming a ceramic carrier comprising a first side and a second side opposite the first side;
forming a first metal layer over the first side of the ceramic carrier;
forming a second metal layer over the second side of the ceramic carrier; and
forming a cooling structure over the second metal layer; wherein the cooling structure is formed from the same metal as the second metal layer;
wherein the cooling structure is configured to form a structure selected from a group consisting of a pin structure, a fin structure, and combinations thereof;

disposing a chip on the first metal layer, wherein the chip is electrically coupled to the first metal layer;
forming a second substrate, comprising:
forming a ceramic carrier comprising a first side and a second side opposite the first side;
forming a first metal layer over the first side of the ceramic carrier;
forming a second metal layer over the second side of the ceramic carrier; and
forming a cooling structure into or over on the second metal layer;
wherein the cooling structure is formed from the same metal as the second metal layer;

wherein the chip is sandwiched between the first substrate and the second substrate and furthermore directly coupled to the second substrate, wherein the chip is furthermore electrically coupled to the first metal layer of the second substrate.

11. The method of claim 10 , further comprising:
forming an encapsulation material at least partially over the sidewalls of the chip and at least one of the first substrate and/or the second substrate.

12. The method of claim 11 ,
wherein the second metal layer of the at least one of the first substrate and/or the second substrate is at least partially exposed.

13. The method of claim 10 , further comprising: forming an encapsulation material at least partially over the sidewalls of the chip and the first substrate and the second substrate.

14. The method of claim 13 ,
wherein the second metal layer of the first substrate and the second metal layer of the second substrate are at least partially exposed.

15. The method of claim 10 , wherein the first metal layer comprises a first side and a second side opposite the first side, wherein the first side of the first metal layer is disposed over the chip carrier, and further comprising a thermal interconnect disposed on the second side of the first metal layer, wherein the thermal interconnect is configured to directly contact a chip.

16. The method of claim 10 , wherein the second metal layer and the cooling structure are formed of a single, continuous piece of material.

17. The method of claim 10 , wherein the first metal layer is formed from the same metal as the second metal layer.

Assignees

• Infineon Technologies Ag

Inventors

• Hable Wolfram
• Grassmann Andreas
• Winter Frank
• Geitner Ottmar
• Schwarz Alexander
• Herbrandt Alexander

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W40/47

  by flowing liquids, e.g. forced water cooling · CPC title

• H10W40/43

  by flowing gases, e.g. forced air cooling · CPC title

• H10W76/138

  having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type · CPC title