RRAM cell bottom electrode formation

Patent metadata

Field	Value
Publication number	US-9577191-B2
Application number	US-201414242983-A
Country	US
Kind code	B2
Filing date	Apr 2, 2014
Priority date	Apr 2, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

First claim

What is claimed is:

1. A method of forming a resistive random access memory (RRAM) cell, comprising:
forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process that forms at least a top portion of the bottom electrode;
forming a dielectric data storage layer having a variable resistance onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode;
forming a top electrode over the dielectric data storage layer; and
forming an upper metal interconnect layer over the top electrode.

2. The method of claim 1 , wherein forming the bottom electrode comprises:
depositing a first bottom electrode layer using a physical vapor deposition (PVD) process; and
depositing a second bottom electrode layer onto and in direct contact with the first bottom electrode layer using the ALD process.

3. The method of claim 2 , wherein the second bottom electrode layer has a thickness in a range of between approximately 15 angstroms and approximately 30 angstroms.

4. The method of claim 1 , wherein the bottom electrode comprises titanium nitride (TiN).

5. The method of claim 4 , wherein the dielectric data storage layer comprises hafnium oxide (HfOx).

6. The method of claim 1 , wherein the ALD process comprises a plasma enhanced ALD (PEALD) process.

7. The method of claim 1 , wherein the bottom electrode has an oxygen concentration of approximately 2.5% at an interface between the bottom electrode and the dielectric data storage layer.

8. The method of claim 1 , wherein the dielectric data storage layer is formed using a separate atomic layer deposition (ALD) process.

9. The method of claim 1 , wherein the dielectric data storage layer is configured to undergo a reversible change between a high resistance state and a low resistance state depending on a voltage applied to the bottom electrode or the top electrode.

10. A method of forming a resistive random access memory (RRAM) cell, comprising:
forming a bottom dielectric layer onto a lower metal interconnect layer surrounded by an inter-level dielectric (ILD) layer;
forming a diffusion barrier layer onto the lower metal interconnect layer and the bottom dielectric layer;
forming a bottom electrode onto the diffusion barrier layer using an atomic layer deposition (ALD) process that forms at least a top portion of the bottom electrode;
forming a dielectric data storage layer having a variable resistance onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode;
forming a capping layer onto the dielectric data storage layer;
forming a top electrode onto the dielectric data storage layer; and
forming an upper metal interconnect layer onto the top electrode.

11. The method of claim 10 , wherein forming the bottom electrode comprises:
depositing a first bottom electrode layer using a physical vapor deposition (PVD) process; and
depositing a second bottom electrode layer onto and in direct contact with the first bottom electrode layer using the ALD process.

12. The method of claim 11 , wherein the second bottom electrode layer has a thickness in a range of between approximately 15 angstroms and approximately 30 angstroms.

13. The method of claim 10 , wherein the bottom electrode comprises titanium nitride (TiN).

14. The method of claim 13 , wherein the dielectric data storage layer comprises hafnium oxide (HfOx).

15. The method of claim 10 , wherein the bottom electrode has an oxygen concentration of approximately 2.5% at an interface between the bottom electrode and the dielectric data storage layer.

16. The method of claim 10 , wherein the dielectric data storage layer is configured to undergo a reversible change between a high resistance state and a low resistance state depending on a voltage applied to the bottom electrode or the top electrode.

17. A method of forming a resistive random access memory (RRAM) cell, comprising:
forming a bottom electrode over a lower metal interconnect layer, by using a physical vapor deposition (PVD) process to form a lower portion of the bottom electrode and an in-situ plasma enhanced atomic layer deposition (PEALD) process to form an overlying upper portion of the bottom electrode;
forming a dielectric data storage layer having a variable resistance onto the upper portion of the bottom electrode in-situ with forming the bottom electrode;
forming a top electrode over the dielectric data storage layer; and
forming an upper metal interconnect layer over the top electrode.

18. The method of claim 17 , wherein the lower portion and the upper portion of the bottom electrode have outermost sidewalls that are aligned with outermost sidewalls of the dielectric data storage layer.

19. The method of claim 17 , wherein the lower portion of the bottom electrode has a greater thickness than the upper portion of the bottom electrode.

20. The method of claim 17 , wherein the lower portion and the upper portion of the bottom electrode have outermost sidewalls that are aligned.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Dang Trinh Hai
• Lin Hsing-Lien
• Cheng Kai-Wen
• Tsai Cheng-Yuan
• Tsai Chia-Shiung
• Lee Ru-Liang

Classifications

• H01L45/1616 Primary

  Electricity · mapped topic

• H01L45/1675

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic