Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar
US-2024419761-A1 · Dec 19, 2024 · US
US9177996B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9177996-B2 |
| Application number | US-201314072611-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 5, 2013 |
| Priority date | Mar 14, 2013 |
| Publication date | Nov 3, 2015 |
| Grant date | Nov 3, 2015 |
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Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging.
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What is claimed is: 1. A method comprising forming a memory structure, wherein the memory structure comprises an insulator layer disposed between two electrode layers; heating the memory structure to a temperature higher than an operating temperature of the memory structure; applying a first voltage to the two electrode layers to form a switching layer from the insulator layer; stopping heating the memory structure. 2. A method as in claim 1 wherein t…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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