Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

Patent metadata

Field	Value
Publication number	US-9576875-B2
Application number	US-201514591014-A
Country	US
Kind code	B2
Filing date	Jan 7, 2015
Priority date	Sep 11, 2012
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

First claim

The invention claimed is:

1. A chip arrangement, comprising
a chip, the chip comprising at least one chip contact at a top side of the chip;
a passivation layer formed over at least one side wall of the chip;
a contact comprising an electrically conductive layer including a first portion disposed on the passivation layer so as to be formed over the at least one sidewall, and a second portion extending over at least a portion of the top side of the chip and over the at least one chip contact,
wherein the electrically conductive layer is in electrical connection with the at least one chip contact and wherein an outer surface of the first portion and the second portion of the electrically conductive layer is exposed.

2. The chip arrangement according to claim 1 ,
wherein the passivation layer comprises a polymer material.

3. The chip arrangement according to claim 1 ,
wherein the passivation layer comprises a thickness of at least about 100 nm.

4. A chip arrangement, comprising
a chip comprising at least one singulated side wall;
a passivation layer formed over the at least one singulated side wall of the chip, wherein the at least one singulated sidewall comprises a series of consecutively adjacent scalloped recesses and wherein the passivation layer is conformally-like disposed over the at least one singulated side wall of the chip,
wherein the passivation layer comprises a thickness of at least about 100 nm.

5. The chip package according to claim 4 ,
wherein the passivation layer comprises a polymer material.

6. A chip package, comprising
a chip comprising at least one chip contact;
a passivation layer formed over at least one side wall of the chip and over a portion of the a top surface of the chip,
at least one contact formed on a portion of the passivation layer disposed over the top surface of the chip and formed on a portion of the passivation layer disposed over the at least one sidewall of the chip, wherein the at least one contact is in electrical connection with the at least one chip contact with an outer surface of the contact being exposed.

7. The chip package according to claim 6 ,
wherein the passivation layer electrically insulates the at least one contact from at least one side wall of the chip.

8. The chip package according to claim 6 ,
wherein the passivation layer comprises a polymer material.

9. The chip package according to claim 6 ,
wherein the passivation layer comprises a thickness of at least about 100 nm.

10. The chip arrangement of claim 1 , wherein the at least one sidewall comprises scalloped recesses and wherein the passivation layer conformally-like disposed over at least one side wall of the chip.

11. The chip arrangement of claim 4 , wherein the at least one singulated sidewall is obtained by an etch process comprising:
forming a hole in a carrier comprising the chip, wherein forming a hole in the carrier comprises:
selectively removing carrier material, thereby forming a cavity in the carrier,
forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall, wherein forming the hole in the carrier comprises forming the hole through the carrier wherein the chip is separated from the carrier, and wherein the at least one cavity side wall comprises a side wall of the chip;

subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Assignees

• Infineon Technologies Ag

Inventors

• Hess Reinhard
• Umminger Katharina
• Maier Gabriel
• Menath Markus
• Mackh Gunther
• Eder Hannes
• Heinrich Alexander

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title

• H10W72/941

  Dispositions of bond pads · CPC title

• H10W70/652

  Cross-sectional shapes · CPC title