Efficient skew scheduling methodology for performance and low power of a clock-mesh implementation

Patent metadata

Field	Value
Publication number	US-9571074-B2
Application number	US-201514814495-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Oct 27, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

According to one aspect, a method may include receiving a circuit model that includes a clock mesh that controls each of a plurality of logic circuits by inputting a respective clock signal to an end-point of each logic circuit. The method may include providing an incremental latency adjustment to the circuit model by determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule. And, for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of an end-point by a quantized amount. Further, for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of an end-point that is associated by a quantized amount. The method may also include repeating, the step of providing an incremental timing update. The method may include performing a timing evaluation upon the circuit model.

First claim

What is claimed is:

1. A method of adjusting clock skews, the method comprising:
receiving a circuit model that includes logic circuits at least partially controlled by a clock network, wherein the clock network, at least partially, controls each of the logic circuits by inputting a respective clock signal to an end-point of a respective logic circuit;
providing an incremental latency adjustment to the circuit model by:
for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of a respective end-point by a first quantized amount, up to a maximum push threshold,
for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of a respective end-point that is associated by a second quantized amount, up to a maximum pull threshold, and
reevaluating at least one of the negative front slack and the negative back-slack for each end-point in the circuit model after adjusting all the clock skew schedules of the one-or more end-points; and

repeating, a plurality of times, the step of providing the incremental latency adjustment to the circuit model.

2. The method of claim 1 , wherein providing the latency adjustment update to the circuit model includes avoiding push/pull adjustment clock latency conflicts between end-points by adjusting the end-points associated with the negative front slack, and adjusting the end-points associated with the negative back slack in separate steps.

3. The method of claim 1 , wherein adjusting the clock skew of a respective end-point includes:
provisionally estimating a new slack associated with the end-point after adjusting the clock-skew schedule of the end-point, and not performing either dynamic timing verification, static timing analysis, nor both; and
wherein repeating the step of providing the latency adjustment update to the circuit model includes determining the end-points that are the candidates for adjustment based upon the provisionally estimated new slack.

4. The method of claim 1 , wherein for each end-point that is associated with a negative back slack, adjusting the clock skew schedule of a respective end-point that is associated with a negative back slack by a quantized amount includes:
if both a front slack and a back slack are negative, adjusting the clock skew schedule to, at least partially, equalize the front slack and the back slack within the quantization step size.

5. The method of claim 1 , wherein repeating, a plurality of times, the step of providing the latency adjustment update to the circuit model includes:
effectively performing multi-stage look ahead scheduling of clock slack for a plurality of pipeline stages.

6. The method of claim 1 , wherein the quantized amount by which the clock skew schedule is adjusted is a delay associated with a skew buffer circuit; and
wherein the maximum pull threshold is smaller than the maximum push threshold.

7. The method of claim 1 , wherein repeating, a plurality of times, the step of providing the latency adjustment update to the circuit model comprises:
co-optimizing the useful-skew scheduling with a physical synthesis optimization so as to reorganize the circuit model in a direction of timing convergence.

8. The method of claim 1 , wherein determining one or more end-points that are candidates for adjustment of the respective end-point's clock skew schedule includes:
categorizing end-points into one or at least two categories, wherein the at least two categories includes Pull Candidates, and Push Candidates.

9. The method of claim 1 , wherein providing the latency adjustment update to the circuit model includes:
selecting a preference between worst-negative-slack and total-negative-slack via the selection of the slack threshold to skew and maximum push/pull limits.

10. A computer program product for adjusting clock skew schedules of a digital circuit, the computer program product being tangibly embodied on a computer-readable medium and including executable code that, when executed, is configured to cause a data processing apparatus to:
receive a circuit model that includes logic circuits at least partially controlled by a clock network, wherein the clock network, at least partially, controls each of the logic circuits by inputting a respective clock signal to an end-point of a respective logic circuit; and
provide an incremental timing update to the circuit model by:
for each end-point that is associated with a negative front slack, adjust a clock skew schedule of a respective end-point that is associated with negative front slack by a first quantized amount, up to a maximum push threshold,
for each end-point that is associated with a negative back slack, adjust the clock skew schedule of a respective end-point that is associated with negative back slack by a second quantized amount, up to a maximum pull threshold, and
reevaluate at least one of the negative front slack and at least one of the negative back slack for each end-point in the circuit model after adjusting all the clock skew schedules of the one-or more end-points.

11. The computer program product of claim 10 , wherein the executable code that, when executed, is configured to cause the data processing apparatus to:
not perform a separate timing update after a clock skew schedule is adjusted for each respective end-point.

12. The method of claim 1 , wherein adjusting a clock skew schedule includes adjusting a clock skew schedule based upon a reduction in power consumption.

13. The method of claim 1 , wherein adjusting a clock skew schedule for setup reduction includes adjusting a clock skew schedule to improve, at least in part, hold timings.

14. The method of claim 1 , wherein adjusting a clock skew schedule comprises adjusting a clock skew schedule for hold reduction.

15. The method of claim 14 , wherein adjusting a clock skew schedule comprises scheduling for hold reduction to improve, at least in part, setup timings.

Assignees

• Chowdhury Ahsan H
• Millar Brian
• Fedor John M
• Lewis Michael P
• Samsung Electronics Co Ltd

Inventors

• Chowdhury Ahsan H
• Millar Brian
• Fedor John M
• Lewis Michael P

Classifications

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• H03K5/05 Primary

  by the use of clock signals or other time reference signals · CPC title