Complementary output generator module

Patent metadata

Field	Value
Publication number	US-9310828-B2
Application number	US-201314080322-A
Country	US
Kind code	B2
Filing date	Nov 14, 2013
Priority date	Nov 15, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.

First claim

What is claimed is:

1. A complementary output generator module for a microcontroller, wherein the complimentary output generator is configurable through a processing core of the microcontroller and comprises:
a clock input coupled to a clock source;
a plurality of rising event inputs that are programmably selectable, wherein at least one of the selected rising event inputs initiates a rising event signal synchronous with the clock source when at least one rising event occurs at a respective selected one of the rising event inputs;
a plurality of falling event inputs that are programmably selectable, wherein at least one of the selected falling event inputs initiates a falling event signal synchronous with the clock source when at least one falling event occurs at a respective selected one of the falling event inputs; and
a plurality of outputs, wherein
a first one of the plurality of outputs asserts a first output drive signal upon detection of the rising event signal until detection of the falling event signal, and
a second one of the plurality of outputs asserts a second output drive signal upon detection of the falling event signal until detection of a next rising event signal.

2. The complementary output generator module according to claim 1 , further comprising a clock multiplexer coupled between the clock input and a plurality of clock sources, wherein the clock multiplexer is adapted to select a one of the plurality of clock sources.

3. The complementary output generator module according to claim 1 , further comprising a rising event blanking time circuit for inhibiting the rising event from generating the rising event signal until after the rising event blanking time circuit has timed out.

4. The complementary output generator module according to claim 3 , wherein the rising event blanking time circuit comprises:
a counter coupled to the clock source;
a comparator coupled to the counter; and
a blanking time register coupled to the comparator.

5. The complementary output generator module according to claim 3 , wherein the rising event blanking time circuit comprises:
a plurality of series connected unit delay elements; and
a multiplexer having inputs coupled to respective ones of the plurality of series connected unit delay elements.

6. The complementary output generator module according to claim 1 , further comprising a falling event blanking time circuit for inhibiting the falling event from generating the falling event signal until after the falling event blanking time circuit has timed out.

7. The complementary output generator module according to claim 6 , wherein the falling event blanking time circuit comprises:
a counter coupled to the clock source;
a comparator coupled to the counter; and
a blanking time register coupled to the comparator.

8. The complementary output generator module according to claim 6 , wherein the falling event blanking time circuit comprises:
a plurality of series connected unit delay elements; and
a multiplexer having inputs coupled to respective ones of the plurality of series connected unit delay elements.

9. The complementary output generator module according to claim 1 , further comprising a rising event deadband time circuit for inhibiting the second output drive signal until after the rising event deadband time circuit has timed out.

10. The complementary output generator module according to claim 9 , wherein the rising event deadband time circuit comprises:
a counter coupled to the clock source;
a comparator coupled to the counter; and
a deadband time register coupled to the comparator.

11. The complementary output generator module according to claim 9 , wherein the rising event deadband time circuit comprises:
a plurality of series connected unit time delay elements; and
a multiplexer having inputs coupled to respective ones of the plurality of series connected unit delay elements.

12. The complementary output generator module according to claim 11 , wherein each unit time delay element provides a fixed time delay.

13. The complementary output generator module according to claim 12 , wherein the fixed time delay is about five nanoseconds.

14. The complementary output generator module according to claim 1 , further comprising a falling event deadband time circuit for inhibiting the first output drive signal until after the falling event deadband time circuit has timed out.

15. The complementary output generator module according to claim 14 , wherein the falling event deadband time circuit comprises:
a counter coupled to the clock source;
a comparator coupled to the counter; and
a deadband time register coupled to the comparator.

16. The complementary output generator module according to claim 14 , wherein the falling event deadband time circuit comprises:
a plurality of series connected unit time delay elements; and
a multiplexer having inputs coupled to respective ones of the plurality of series connected unit delay elements.

17. The complementary output generator module according to claim 16 , wherein each unit time delay element provides a fixed time delay.

18. The complementary output generator module according to claim 1 , further comprising a plurality of output polarity reversing circuits, each one of the plurality of output polarity reversing circuits is coupled to a respective one of the plurality of outputs, wherein when a first logic level is applied to the output polarity reversing circuits the respective ones of the plurality of outputs provide a non-inverted output drive signal and when a second logic level is applied to the output polarity reversing circuits the respective ones of the plurality of outputs provide an inverted output drive signal.

19. The complementary output generator module according to claim 1 , further comprising a plurality of output steering multiplexers, wherein the plurality of output steering multiplexers couples respective ones of the plurality of outputs to either a respective signal, a logic high, a logic low, or a high impedance.

20. The complementary output generator module according to claim 19 , wherein the plurality of output steering multiplexers changes coupling of signals to the plurality of outputs substantially immediately.

21. The complementary output generator module according to claim 19 , wherein the plurality of output steering multiplexers changes coupling of signals to the plurality of outputs in synchronization with a next rising event signal.

22. The complementary output generator module according to claim 1 , further comprising a pulse width modulation (PWM) generator having an output coupled to the rising and falling event inputs.

23. The complementary output generator module according to claim 1 , wherein the complementary output generator module is configured in a half-bridge mode.

24. The complementary output generator module according to claim 1 , wherein the complementary output generator module is configured in a push-pull mode.

25. The complementary output generator module according to claim 1 , wherein the complementary output generator module is configured in a forward full-bridge mode.

26. The complementary output generator module according to claim 1 , wherein the complementary output generator module is configured in a reverse full-bridge mode.

27. The complementary output generator module according to claim 1 , wherein

Assignees

• Microchip Tech Inc

Inventors

• Steedman Sean Stacy
• Lundstrum Zeke
• Groza Cristian Nicolae
• Copacian Sebastian Dan
• Darmawaskita Hartono

Classifications

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H03K5/05 Primary

  by the use of clock signals or other time reference signals · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• G06F1/06 Primary

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• H03K5/1515

  non-overlapping · CPC title