Slew based process and bias monitors and related methods

Patent metadata

Field	Value
Publication number	US-9319034-B2
Application number	US-201514755689-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Nov 15, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

First claim

What is claimed is:

1. An integrated circuit, comprising:
at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor;
a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal;
a counter configured to generate a count value corresponding to the duration of the first pulse;
a pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse; wherein
the duration of the extended pulse is proportional to the duration of the first pulse;
the at least one slew generator circuit includes an n-channel reference transistor and a p-channel reference transistor, each of the n-channel reference transistor and the p-channel transistor having a first threshold voltage setting; and
the integrated circuit includes other circuits that include transistors fabricated with the same process as the n-channel and p-channel reference transistors, the other circuits having transistors wherein at least some transistors have a second threshold voltage setting.

2. The integrated circuit of claim 1 , wherein:
the at least one reference transistor includes a heavily doped region to which a body bias is coupled.

3. The integrated circuit of claim 1 , wherein:
the at least one reference transistor further includes a body region, a substantially undoped channel and a doped screening region formed under the substantially undoped channel and above the body region, the screening region being doped to a higher concentration than the body region.

4. The integrated circuit of claim 1 , further including:
circuits configured to adjust the operating characteristics of other transistors of the integrated circuit based on the duration of the first pulse, the characteristic selected from the group of: transistor speed and transistor power consumption.

5. The integrated circuit of claim 1 , wherein:
the pulse extender receives an input pulse signal at a first pulse, and generates an extended pulse signal as a digital multiplier of the first pulse, the pulse extender further including a frequency divider.

6. The integrated circuit of claim 1 , further including:
a pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse having a duration proportional to the first pulse; and
the counter increments a count value during the duration of the extended pulse.

7. The integrated circuit of claim 1 , wherein
the at least one slew generator circuit includes
an n-channel slew generator circuit configured to generate the first signal, and a slew rate of the first signal varies according to the operation of an n-channel reference transistor, and
a p-channel slew generator circuit configured to generate a second signal, and a slew rate of the second signal varies according the operation of a p-channel reference transistor;
wherein the integrated circuit includes other circuits that include transistors fabricated with the same process as the n-channel and p-channel reference transistors.

8. The integrated circuit of claim 1 , further comprising:
at least one body bias control circuit configured to generate a body bias voltage for other transistors of the integrated circuit that varies in response to the count value.

9. An integrated circuit, comprising:
at least one slew generator circuit comprising at least one reference transistor, the slew generator circuit configured to generate at least a first slew signal having a slew rate that varies according to characteristics of the reference transistor;
a pulse generator circuit coupled to receive the first slew signal and configured to drive a pulse signal to a first value when a level of the first slew signal is within first and second limits, and configured to drive the pulse signal to a second value when the level of the first slew signal is outside of the first and second limits;
a counter configured to generate a count value corresponding to a duration of the pulse signal at the first value;
a digital pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse, the duration of the extended pulse being proportional to the duration of the first pulse being at the first value; and
at least one body bias control circuit configured to generate a body bias voltage for at least some portions of the integrated circuit in response to the duration of the extended pulse.

10. The integrated circuit of claim 9 , wherein:
the at least one slew generator comprises a load capacitor coupled to the source-drain path of the at least one reference transistor;
the pulse generator circuit includes
a first comparator having one input coupled to receive a voltage from the load capacitor, and a second input coupled to a first limit voltage,
a second comparator having one input coupled to receive the voltage from the load capacitor, and a second input coupled to a second limit voltage, and
logic circuits coupled to outputs of the first and second comparators, and configured to output the pulse signal.

11. The integrated circuit of claim 9 , wherein:
the at least one reference transistor includes a body region and a screening region formed under a substantially undoped channel, the screening region positioned between the substantially undoped channel and the body region, with the screening region being doped to a higher concentration than body region.

12. The integrated circuit of claim 9 , wherein:
the at least one slew generator circuit includes
an n-channel slew generator circuit configured to generate the first pulse signal with a pulse having a duration that varies according to the operation of an n-channel reference transistor, and
a p-channel slew generator circuit configured to generate a second pulse signal having a pulse duration that varies according the operation of a p-channel reference transistor; wherein
the integrated circuit includes other circuits that include transistors fabricated with the same process as the n-channel and p-channel reference transistors.

13. An integrated circuit, comprising:
at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor;
a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal;
a counter configured to generate a count value corresponding to a duration of the first pulse;
a pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse;
wherein the duration of the extended pulse is proportional to the duration of the first pulse; and
wherein the pulse extender receives an input pulse signal at a first pulse, and generates an extended pulse signal as a digital multiplier of the first pulse, the pulse extender further including a frequency divider.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Kidd David A
• Boling Edward J
• Agrawal Vineet
• Leshner Samuel
• Kuo Augustine
• Lee Sang-Soo
• Chen Chao-Wu

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H03K5/05 Primary

  by the use of clock signals or other time reference signals · CPC title

• H01L22/34

  Electricity · mapped topic

• H03K5/04

  by increasing duration; by decreasing duration · CPC title